AD9633 datasheet(39/42 Pages) AD

39 / 42 page

AD9633

Data Sheet

Rev. B | Page 38 of 41

than the value of Bits[2:0], Register 0x0B. See Table 19 for more

information.

Table 19. Input Clock Phase Adjust Options

Input Clock Phase

Adjust, Bits[6:4]

Number of Input Clock Cycles of

Phase Delay

000 (Default)

001

010

011

100

101

110

111

Bits[3:0]—Output Clock Phase Adjust

Table 20. Output Clock Phase Adjust Options

Output Clock (DCO),

Phase Adjust, Bits[3:0]

DCO Phase Adjustment (Degrees

Relative to D0±x/D1±x Edge)

0000

0001

0010

120

0011 (Default)

180

0100

240

0101

300

0110

360

0111

420

1000

480

1001

540

1010

600

1011

660

Serial Output Data Control (Register 0x21)

The serial output data control register is used to program the

AD9633 in various output data modes depending upon the data

capture solution. Table 21 describes the various serialization

options available in the AD9633.

Resolution/Sample Rate Override (Register 0x100)

This register is designed to allow the user to downgrade the device

(that is, establish lower power) for applications that do not require

full sample rate. Settings in this register are not initialized until Bit 0

of the transfer register (Register 0xFF) is set to 1.

This function does not affect the sample rate; it affects the

maximum sample rate capability of the ADC, as well as the

resolution.

User I/O Control 2 (Register 0x101)

Bits[7:1]—Open

Bit 0—SDIO Pull-Down

Bit 0 can be set to disable the internal 30 kΩ pull-down on the

SDIO pin, which can be used to limit the loading when many

devices are connected to the SPI bus.

User I/O Control 3 (Register 0x102)

Bits[7:4]—Open

Bit 3—VCM Power-Down

Bit 3 can be set high to power down the internal VCM generator.

This feature is used when applying an external reference.

Bits[2:0]—Open

Table 21. SPI Register Options

Serialization Options Selected

Contents

Serial Output Number of

Bits (SONB)

Frame Mode

Serial Data Mode

DCO Multiplier

Timing Diagram

0x32

12-bit

1×

DDR two-lane bytewise

3 × fS

Figure 2 (default setting)

0x22

12-bit

1×

DDR two-lane bitwise

3 × fS

Figure 2

0x12

12-bit

1×

SDR two-lane bytewise

6 × fS

Figure 2

0x02

12-bit

1×

SDR two-lane bitwise

6 × fS

Figure 2

0x36

12-bit

2×

DDR two-lane bytewise

3 × fS

Figure 4

0x26

12-bit

2×

DDR two-lane bitwise

3 × fS

Figure 4

0x16

12-bit

2×

SDR two-lane bytewise

6 × fS

Figure 4

0x06

12-bit

2×

SDR two-lane bitwise

6 × fS

Figure 4

0x42

12-bit

1×

DDR one-lane

6 × fS

Figure 6

0x33

10-bit

1×

DDR two-lane bytewise

2.5 × fS

Figure 3

0x23

10-bit

1×

DDR two-lane bitwise

2.5 × fS

Figure 3

0x13

10-bit

1×

SDR two-lane bytewise

5 × fS

Figure 3

0x03

10-bit

1×

SDR two-lane bitwise

5 × fS

Figure 3

0x37

10-bit

2×

DDR two-lane bytewise

2.5 × fS

Figure 5

0x27

10-bit

2×

DDR two-lane bitwise

2.5 × fS

Figure 5

0x17

10-bit

2×

SDR two-lane bytewise

5 × fS

Figure 5

0x07

10-bit

2×

SDR two-lane bitwise

5 × fS

Figure 5

0x43

10-bit

1×

DDR one-lane

5 × fS

Figure 7

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