AD9467 datasheet(24/34 Pages) AD

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AD9467

Data Sheet

Rev. D | Page 22 of 32

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9467 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled to the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

and require no additional biasing.

Figure 58 shows a preferred method for clocking the AD9467. The

low jitter clock source is converted from a single-ended signal

to a differential signal using an RF transformer. The back-to-

back Schottky diodes across the secondary transformer limit

clock excursions into the AD9467 to approximately 0.8 V p-p

differential. This helps prevent the large voltage swings of the

clock from feeding through to other portions of the AD9467,

and it preserves the fast rise and fall times of the signal, which

are critical to low jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSM2812

50Ω

100Ω

CLK–

CLK+

ADC

XFMR

MINI-CIRCUITS®

ADT1-1WT, 1:1 Z

CLOCK INPUT

Figure 58. Transformer-Coupled Differential Clock

Another option is to ac-couple a differential PECL or LVDS

signal to the sample clock input pins, as shown in Figure 59 and

Figure 60. The AD9510/AD9511/AD9512/AD9513/AD9514/

AD9515/AD9516/AD9517/AD9520/AD9522/AD9523/AD9524

family of clock drivers offers excellent jitter performance.

100

Ω

0.1µF

240

Ω

240

Ω

Ω1

CLK

150

Ω RESISTORS ARE OPTIONAL.

CLK–

CLK+

ADC

PECL DRIVER

CLOCK INPUT

Figure 59. Differential PECL Sample Clock

0Ω

0.1µF

50Ω1

LVDS DRIVER

50Ω1

CLK

50Ω RESISTORS ARE OPTIONAL.

CLK–

CLK+

ADC

CLOCK INPUT

Figure 60. Differential LVDS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9467 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9467.

Any changes to the sampling frequency require several clock

cycles to allow the internal timing to acquire and lock at the

new sampling rate.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) due only to aperture jitter (tJ) can be calculated by

SNR = 20 × log 10(2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 61).

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9467.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or other methods), it should

be retimed by the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs.

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

Figure 61. Ideal SNR vs. Input Frequency and Jitter

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