Data Sheet

AD9467

Rev. D | Page 7 of 32

SWITCHING SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V

internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted.

Table 4.

AD9467BCPZ-200

AD9467BCPZ-250

Parameter1

Temp

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK2

Clock Rate

Full

50

200

50

250

MSPS

Full

2.5

2

ns

Full

2.5

2

ns

OUTPUT PARAMETERS2, 3

25°C

3

3

ns

25°C

200

200

ps

25°C

200

200

ps

25°C

3

3

ns

Full

−200

+200

−200

+200

ps

Wake-UpTime (Power-Down)

Full

100

100

ms

Pipeline Latency

Full

16

16

Clock cycles

APERTURE

25°C

1.2

1.2

ns

Aperture Uncertainty (Jitter)

25°C

60

60

fs rms

Out-of-Range Recovery Time

25°C

1

1

Clock cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2

Can be adjusted via the SPI interface.

3

Measurements were made using a part soldered to FR-4 material.

Timing Diagrams

N – 1

N + 1

N + 2

N + 3

N + 4

N + 5

N

1/fs

CLK+

CLK–

DCO+

DCO–

D15+/D14+ (MSB)

D15–/D14– (MSB)

D1+/D0+ (LSB)

D1–/D0– (LSB)

VIN±

D15

D14

N – 16

N – 16

N – 15

N – 15

N – 14

N – 13

N – 12

N – 11

N – 10

N – 10

N – 16

N – 16

N – 15

N – 15

N – 14

N – 13

N – 12

N – 11

N – 10

N – 10

D1

D0

.

.

.

Figure 2. 16-Bit Output Data Timing