AD9253

Data Sheet

Rev. B | Page 12 of 40

Pin No.

Mnemonic

Description

44

SYNC

Digital Input. SYNC input to clock divider.

47

VIN−C

ADC C Analog Input Complement.

48

VIN+C

ADC C Analog Input True.

1

Output channel assignments are shown first for default two-lane mode. If one-lane mode is used, output channel assignments change as indicated in parenthesis.

Register 0x21 Bits[6:4] invoke one-lane mode.