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AD9253

Data Sheet

Rev. B | Page 38 of 40

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9253 as a system,

it is recommended that the designer become familiar with these

guidelines, which describes the special circuit connections and

layout requirements that are needed for certain pins.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9253, it is recommended

that two separate 1.8 V supplies be used. Use one supply for

analog (AVDD); use a separate supply for the digital outputs

(DRVDD). For both AVDD and DRVDD, several different

decoupling capacitors should be used to cover both high and

low frequencies. Place these capacitors close to the point of

entry at the PCB level and close to the pins of the part, with

minimal trace length.

A single PCB ground plane should be sufficient when using the

AD9253. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

CLOCK STABILITY CONSIDERATIONS

When powered on, the AD9253 enters an initialization phase

during which an internal state machine sets up the biases and

the registers for proper operation. During the initialization

process, the AD9253 needs a stable clock. If the ADC clock

source is not present or not stable during ADC power-up, it

disrupts the state machine and causes the ADC to start up in an

unknown state. To correct this, an initialization sequence must

be reinvoked after the ADC clock is stable by issuing a digital

reset via Register 0x08. In the default configuration (internal

VREF, ac-coupled input) where VREF and VCM are supplied by the

ADC itself, a stable clock during power-up is sufficient. In the

case where VREF and/or VCM are supplied by an external source,

these, too, must be stable at power-up; otherwise, a subsequent

digital reset via Register 0x08 is needed. The pseudo code

sequence for a digital reset is as follows:

SPI_Write (0x08, 0x03);

Digital Reset

SPI_Write (0x08, 0x00);

Can be asserted as

soon as the next

SPI instruction,

normal operation

resumes after 2.9

million sample

clock cycles, ADC

outputs 0s until

the reset is

complete.

EXPOSED PAD THERMAL HEAT SLUG

RECOMMENDATIONS

It is required that the exposed pad on the underside of the ADC

be connected to analog ground (AGND) to achieve the best

electrical and thermal performance of the AD9253. An exposed

continuous copper plane on the PCB should mate to the

AD9253 exposed pad, Pin 0. The copper plane should have

several vias to achieve the lowest possible resistive thermal path

for heat dissipation to flow through the bottom of the PCB.

These vias should be solder-filled or plugged.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a

silkscreen on the PCB into several uniform sections. This provides

several tie points between the ADC and PCB during the reflow

process, whereas using one continuous plane with no partitions

only guarantees one tie point. See Figure 75 for a PCB layout

example. For detailed information on packaging and the PCB

layout of chip scale packages, see the AN-772 Application Note,

A Design and Manufacturing Guide for the Lead Frame Chip

Scale Package (LFCSP), at www.analog.com.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 75. Typical PCB Layout

VCM

The VCM pin should be decoupled to ground with a 0.1 μF

capacitor.

REFERENCE DECOUPLING

The VREF pin should be externally decoupled to ground with a

low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF

ceramic capacitor.

SPI PORT

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9253 to keep these signals from transitioning at the con-

verter inputs during critical sampling periods.

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