Data Sheet

AD9681

Rev. C | Page 11 of 40

FCO–1, FCO–2

DCO+1, DCO+2

CLK+

VIN±x1, VIN±x2

CLK–

DCO–1, DCO–2

FCO+1, FCO+2

D10

N – 17

MSB

N – 17

D9

N – 17

D8

N – 17

D7

N – 17

D6

N – 17

D5

N – 17

D4

N – 17

D3

N – 17

D2

N – 17

D1

N – 17

D0

N – 17

MSB

N – 16

D10

N – 16

N – 1

N

D0–x/D1–x

D0+x/D1+x

Figure 8. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode (See Table 8 for One-Lane Channel Assignments)

SYNC

CLK+

Figure 9. SYNC Input Timing Requirements