AD9681 datasheet(39/41 Pages) AD

39 / 41 page

AD9681

Data Sheet

Rev. C | Page 38 of 40

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting the design and layout of the AD9681 as a system,

it is recommended that the designer become familiar with these

guidelines, which describe the special circuit connections and

layout requirements that are needed for certain pins.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9681, it is recommended

that two separate 1.8 V supplies be used. Use one supply for

analog (AVDD); use a separate supply for the digital outputs

(DRVDD). For both AVDD and DRVDD, use several different

decoupling capacitors for both high and low frequencies. Place

these capacitors near the point of entry at the PCB level and near

the pins of the device, with minimal trace length.

A single PCB ground plane is typically sufficient when using the

AD9681. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

BOARD LAYOUT CONSIDERATIONS

For optimal performance, give special consideration to the

AD9681 board layout. The high channel count and small foot-

print of the AD9681 create a dense configuration that must be

managed for matters relating to crosstalk and switching noise.

Sources of Coupling

Trace pairs interfere with each other by inductive coupling and

capacitive coupling. Use the following guidelines:



Inductive coupling is current induced in a trace by a changing

magnetic field from an adjacent trace, caused by its changing

current flow. Mitigate this effect by making traces orthogonal

to each other whenever possible and by increasing the

distance between them.



Capacitive coupling is charge induced in a trace by the

changing electric field of an adjacent trace. This effect can

be mitigated by minimizing facing areas, increasing the

distance between traces, or changing dielectric properties.



Through-vias are particularly good conduits for both types

of coupling and must be used carefully.



Adjacent trace runs on the same layer may cause unbalanced

coupling between channels.



Traces on one layer should be separated by a plane (ac

ground) from the traces on another layer. Significant

coupling occurs through gaps in that plane, such as the

setback around through-vias.

Crosstalk Between Inputs

To avoid crosstalk between inputs, consider the following

guidelines:



When routing inputs, sequentially alternate input channels

on the top and bottom (or other layer) of the board.



Ensure that the top channels have no vias within 5 mm of

any other input channel via.



For bottom channels, use a via-in-pad to minimize top-

metal coupling between channels.



Avoid running input traces parallel with each other that are

nearer than 2 mm apart.



When possible, lay out traces orthogonal to each other and

to any other traces that are not dc.



Secondhand or indirect coupling may occur through

nonrelated dc traces that bridge the distance between two

traces or vias.

Coupling of Digital Output Switching Noise to Analog

Inputs and Clock

To avoid the coupling of digital output switching noise to the

analog inputs and the clock, use the following guidelines:



Vias on the outputs are a main conduit of noise to the vias

on the inputs. Maintain 5 mm of separation between any

output via and any input via.



Place the encode clock traces on the top surface. Vias are

not recommended in the clock traces. However, if they are

required, ensure that there are no clock trace vias within

5 mm of any input via or output via.



Place output surface traces (not imbedded between planes)

orthogonal to one another as much as possible. Avoid

parallel output to input traces within 2 mm.



Route digital output traces away from the analog input side

of the board.



Coupling among outputs is not a critical issue, but separation

between these high speed output pairs increases the noise

margin of the signals and is good practice.

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