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AD9680 датащи(PDF) 89 Page - Analog Devices |
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AD9680 датащи(HTML) 89 Page - Analog Devices |
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89 / 99 page ![]() Data Sheet AD9680 Rev. C | Page 87 of 97 Reg Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes 0x245 Fast detect (FD) control (local) 0 0 0 0 Force FD_A/ FD_B pins; 0 = normal function; 1 = force to value Force value of FD_A/FD_B pins if force pins is true, this value is output on FD pins 0 Enable fast detect output 0x00 0x247 FD upper threshold LSB (local) Fast detect upper threshold, Bits[7:0] 0x00 0x248 FD upper threshold MSB (local) 0 0 0 Fast detect upper threshold, Bits[12:8] 0x00 0x249 FD lower threshold LSB (local) Fast detect lower threshold, Bits[7:0] 0x00 0x24A FD lower threshold MSB (local) 0 0 0 Fast detect lower threshold, Bits[12:8] 0x00 0x24B FD dwell time LSB (local) Fast detect dwell time, Bits[7:0] 0x00 0x24C FD dwell time MSB (local) Fast detect dwell time, Bits[15:8] 0x00 0x26F Signal monitor synchroniza- tion control 0 0 0 0 0 0 Synchronization mode 00 = disabled 01 = continuous 11 = one shot 0x00 Refer to the Signal Monitor section 0x270 Signal monitor control (local) 0 0 0 0 0 0 Peak detector 0 = disabled 1 = enabled 0 0x00 0x271 Signal Monitor Period Register 0 (local) Signal monitor period, Bits[7:0] 0x80 In deci- mated output clock cycles 0x272 Signal Monitor Period Register 1 (local) Signal monitor period, Bits[15:8] 0x00 In deci- mated output clock cycles 0x273 Signal Monitor Period Register 2 (local) Signal monitor period, Bits[23:16] 0x00 In deci- mated output clock cycles 0x274 Signal monitor result control (local) 0 0 0 Result update 1 = update results (self clear) 0 0 0 Result selection 0 = reserved 1 = peak detector 0x01 0x275 Signal Monitor Result Register 0 (local) Signal monitor result, Bits[7:0] When Register 0x0274[0] = 1, Result Bits[19:7] = Peak Detector Absolute Value[12:0]; Result Bits[6:0] = 0 Read only Updated based on Reg. 0x274[4] |
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