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AD9680

Data Sheet

Rev. C | Page 64 of 97

DIGITAL OUTPUTS

INTRODUCTION TO THE JESD204B INTERFACE

The AD9680 digital outputs are designed to the JEDEC standard

JESD204B, serial interface for data converters. JESD204B is a

protocol to link the AD9680 to a digital processing device over

a serial interface with lane rates of up to 12.5 Gbps. The benefits

of the JESD204B interface over LVDS include a reduction in

required board area for data interface routing, and an ability to

enable smaller packages for converter and logic devices.

JESD204B OVERVIEW

The JESD204B data transmit block assembles the parallel data

from the ADC into frames and uses 8-bit/10-bit encoding as

well as optional scrambling to form serial output data. Lane

synchronization is supported through the use of special control

characters during the initial establishment of the link. Additional

control characters are embedded in the data stream to maintain

synchronization thereafter. A JESD204B receiver is required to

complete the serial link. For additional details on the JESD204B

interface, refer to the JESD204B standard.

The AD9680 JESD204B data transmit block maps up to two

physical ADCs or up to eight virtual converters (when DDCs

are enabled) over a link. A link can be configured to use one,

two, or four JESD204B lanes. The JESD204B specification refers

to a number of parameters to define the link, and these parameters

must match between the JESD204B transmitter (the AD9680

output) and the JESD204B receiver (the logic device input).

The JESD204B link is described according to the following

parameters:

•

L is the number of lanes/converter device (lanes/link)

(AD9680 value = 1, 2, or 4)

•

M is the number of converters/converter device (virtual

converters/link) (AD9680 value = 1, 2, 4, or 8)

•

F is the octets/frame (AD9680 value = 1, 2, 4, 8, or 16)

•

N΄ is the number of bits per sample (JESD204B word size)

(AD9680 value = 8 or 16)

•

N is the converter resolution (AD9680 value = 7 to 16)

•

CS is the number of control bits/sample

(AD9680 value = 0, 1, 2, or 3)

•

K is the number of frames per multiframe

(AD9680 value = 4, 8, 12, 16, 20, 24, 28, or 32 )

•

S is the samples transmitted/single converter/frame cycle

(AD9680 value = set automatically based on L, M, F, and N΄)

•

HD is the high density mode (AD9680 = set automatically

based on L, M, F, and N΄)

•

CF is the number of control words/frame clock cycle/

converter device (AD9680 value = 0)

Figure 155 shows a simplified block diagram of the AD9680

JESD204B link. By default, the AD9680 is configured to use

two converters and four lanes. Converter A data is output to

SERDOUT0± and/or SERDOUT1±, and Converter B is output

to SERDOUT2± and/or SERDOUT3±. The AD9680 allows

other configurations such as combining the outputs of both

converters onto a single lane, or changing the mapping of the

A and B digital output paths. These modes are set up via a quick

configuration register in the SPI register map, along with

additional customizable options.

By default in the AD9680, the 14-bit converter word from each

converter is broken into two octets (eight bits of data). Bit 13

(MSB) through Bit 6 are in the first octet. The second octet

contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits

can be configured as zeros or a pseudorandom number

sequence. The tail bits can also be replaced with control bits

indicating overrange, SYSREF±, or fast detect output.

The two resulting octets can be scrambled. Scrambling is

optional; however, it is recommended to avoid spectral peaks

when transmitting similar digital data patterns. The scrambler

uses a self-synchronizing, polynomial-based algorithm defined

by the equation 1 + x14 + x15. The descrambler in the receiver is

a self-synchronizing version of the scrambler polynomial.

The two octets are then encoded with an 8-bit/10-bit encoder.

The 8-bit/10-bit encoder works by taking eight bits of data (an

octet) and encoding them into a 10-bit symbol. Figure 156

shows how the 14-bit data is taken from the ADC, how the tail

bits are added, how the two octets are scrambled, and how the

octets are encoded into two 10-bit symbols. Figure 156 illustrates

the default data format.

ADC

SYSREF±

SYNCINB±

CONVERTER A

INPUT

CONVERTER B

INPUT

CONVERTER 0

CONVERTER 1

SERDOUT0–,

SERDOUT0+

SERDOUT1–,

SERDOUT1+

SERDOUT2–,

SERDOUT2+

SERDOUT3–,

SERDOUT3+

LANE MUX

AND MAPPING

(SPI

REG 0x5B0,

REG 0x5B2,

REG 0x5B3,

REG 0x5B5,

REG 0x5B6)

JESD204B LINK

CONTROL

(L.M.F)

(SPI REG 0x570)

MUX/

FORMAT

(SPI

REG 0x561,

REG 0x564)

Figure 155. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00)

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