AD9249 datasheet(21/37 Pages) AD

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AD9249

Data Sheet

Rev. 0 | Page 20 of 36

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 41. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515-x/AD9516-x/AD9517-x clock

drivers offer excellent jitter performance.

Figure 41. Differential PECL Sample Clock (Up to 520 MHz)

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 42. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515-x/AD9516-x/

AD9517-x clock drivers offer excellent jitter performance.

Figure 42. Differential LVDS Sample Clock (Up to 520 MHz)

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 μF capacitor (see

Figure 43).

Figure 43. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9249 contains an input clock divider with the ability

to divide the input clock by integer values from 1 to 8.

The AD9249 clock divider can be synchronized using the

external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the

clock divider to be resynchronized on every SYNC signal or

only on the first SYNC signal after the register is written. A

valid SYNC causes the clock divider to reset to its initial state.

This synchronization feature allows the clock dividers of multiple

devices to be aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a variety

of internal timing signals and, as a result, may be sensitive to clock

duty cycle. Commonly, a ±5% tolerance is required on the clock

duty cycle to maintain dynamic performance characteristics.

The AD9249 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock signal

with a nominal 50% duty cycle. This allows the user to provide

a wide range of clock input duty cycles without affecting the per-

formance of the AD9249. Noise and distortion performance are

nearly flat for a wide range of duty cycles with the DCS turned on.

Jitter on the rising edge of the input is still of concern and is not

easily reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates of less than

20 MHz, nominally. The loop has a time constant associated

with it that must be considered in applications in which the

clock rate can change dynamically. A wait time of 1.5 µs to 5 µs

is required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(fA) that is due only to aperture jitter (tJ) is expressed by

SNR Degradation = 20 log10













In this equation, the rms aperture jitter represents the root-sum-

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 44).

Figure 44. Ideal SNR vs. Input Frequency and Jitter

0Ω

0.1µF

240Ω

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

ADC

AD951x

PECL DRIVER

0Ω

0.1µF

50kΩ

CLK–

CLK+

ADC

CLOCK

INPUT

CLOCK

INPUT

AD951x

LVDS DRIVER

OPTIONAL

100Ω

0.1µF

50Ω1

50Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

VCC

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

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