AD9249 datasheet(13/37 Pages) AD

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AD9249

Data Sheet

Rev. 0 | Page 12 of 36

Pin No.

Mnemonic

Description

M12, M11

D−C2, D+C2

Bank 2 Digital Output Complement, Bank 2 Digital Output True.

M10, L10

D−D1, D+D1

Bank 1 Digital Output Complement, Bank 1 Digital Output True.

M9, L9

D−D2, D+D2

Bank 2 Digital Output Complement, Bank 2 Digital Output True.

M4, L4

D−E1, D+E1

Bank 1 Digital Output Complement, Bank 1 Digital Output True.

M3, L3

D−E2, D+E2

Bank 2 Digital Output Complement, Bank 2 Digital Output True.

M1, M2

D−F1, D+F1

Bank 1 Digital Output Complement, Bank 1 Digital Output True.

L1, L2

D−F2, D+F2

Bank 2 Digital Output Complement, Bank 2 Digital Output True.

K1, K2

D−G1, D+G1

Bank 1 Digital Output Complement, Bank 1 Digital Output True.

J1, J2

D−G2, D+G2

Bank 2 Digital Output Complement, Bank 2 Digital Output True.

H1, H2

D−H1, D+H1

Bank 1 Digital Output Complement, Bank 1 Digital Output True.

G1, G2

D−H2, D+H2

Bank 2 Digital Output Complement, Bank 2 Digital Output True.

M6, L6,

M7, L7

DCO−1, DCO+1,

DCO−2, DCO+2

Data Clock Digital Output Complement, Data Clock Digital Output True. DCO±1 is used to

capture D±x1 digital output data; DCO±2 is used to capture D±x2 digital output data.

M5, L5,

M8, L8

FCO−1, FCO+1,

FCO−2, FCO+2

Frame Clock Digital Output Complement, Frame Clock Digital Output True. FCO±1 frames D±x1

digital output data; FCO±2 frames D±x2 digital output data.

F12

SCLK/DTP

Serial Clock (SCLK)/Digital Test Pattern (DTP).

F11

SDIO/DFS

Serial Data Input/Output (SDIO)/Data Format Select (DFS).

E10, F10

CSB1, CSB2

Chip Select Bar. CSB1 enables/disables SPI for eight channels in Bank 1; CSB2 enables/disables

SPI for eight channels in Bank 2.

G10

PDWN

Power-Down.

E12, E11

VIN−A1, VIN+A1