LTC3901

7

3901f

Burst Mode is a registered trademark of Linear Technology Corporation.

In the first period, SDRA goes low (followed by DRVA

going high) and T2 generates a positive voltage at the

LTC3901’s SYNC input. The LTC3901’s ME output then

pulls low. Current flows to the load through MOSFET MF,

T1’s secondary and L1.

In the second period, SDRA goes high and T2 provides

approximately 0V at the LTC3901 SYNC input. This causes

the LTC3901’s ME output to go high and both MOSFET ME

and MF to conduct. This is the free-wheeling period with

T1 secondary winding shorted.

In the third period, SDRB goes low (followed by DRVB

going high) and T2 generates a negative voltage at the

LTC3901’s SYNC input. The LTC3901’s MF output then

pulls low. Current flows to the load through MOSFET ME,

T1’s secondary and L1.

The last period is also a free-wheeling period like the

second period. Both SDRA and SDRB are high and the

LTC3901 forces both MOSFETs ME and MF to conduct.

External MOSFET Protection

A programmable timer and two differential input current

sense comparators are included in the LTC3901 for pro-

tection of the external MOSFETs during power down and

Burst Mode

is incorrect.

When the primary controller is powering down, the

LTC3901 continues to operate by drawing power from the

nous output stops switching and the LTC3901 SYNC input

goes to 0V. Both ME and MF remain on and the decreasing

inductor current continues to flow into the load. Once the

inductor current decreases to zero, it reverses direction,

ues to drop. When the voltage drops below 4.1V, the

LTC3901 shuts down and pulls both ME and MF low. This

causes the inductor current to stop suddenly and the drain

voltage of both MOSFETs to fly high, due to the buildup of

inductor energy. In the absence of a protection timer, if the

inductor energy is high due to a long period of current

reversal, the drain voltage can go above the MOSFET’s

voltage rating and cause damage to the MOSFET.

APPLICATIO S I FOR ATIO

MOSFETs are also kept on for long periods when the

primary controller enters Burst Mode operation. Both ME

and MF stop switching until the primary controller exits

Burst Mode operation. This would also cause the inductor

current to reverse and the drains to fly high.

In both of these situations, the timer and/or current sense

comparator shuts off the drivers before or immediately

after the inductor current reverses direction. This prevents

the buildup of inductor energy.

Timer

The timer circuit (Figure 3) operates by using an external

R-C charging network to program the timeout period. On

every transition at the SYNC input, the chip generates a

200ns pulse to reset the timer capacitor. If the SYNC signal

is missing or incorrect (allowing the timer capacitor volt-

age to go high) it shuts off both drivers once the voltage

reaches the timeout threshold. Figure 4 shows the timer

waveforms.

Figure 4. Timer Waveforms

Figure 3. Timer Circuit

TIMEOUT

32k

470pF

R1

180k

R2

45k

TIMER

RESET

7

16

3901 F03

LTC3901

TMR

TIMER

TIMER RESET

(INTERNAL)

TIMER

SYNC

ME

MF

TIMEOUT

THRESHOLD

3901 F02

0V