DRP3510 datasheet(11/30 Pages) ETC

11 / 30 page

ADVANCE INFORMATION

DRX 3960A

Micronas

4. Control Interface

4.1. I2C Bus Interface

4.1.1. Device and Subaddresses

The DRX 3960A is controlled via the I2C bus slave

interface.

The IC is selected by transmitting one of the

DRX 3960A device addresses. In order to allow up to

three ICs to be connected to a single bus, an address

select pin (ADR_SEL) has been implemented. With

ADR_SEL pulled to high, low, or left open, the

DRX 3960A responds to different device addresses. A

device address pair is defined as a write address and a

read address.

Writing is done by sending the device write address,

followed by the subaddress byte, two address bytes,

and two data bytes. Reading is done by sending the

write device address, followed by the subaddress byte

and two address bytes. Without sending a stop condi-

tion, reading of the addressed data is completed by

sending the device read address and reading two

bytes of data.

Due to the internal architecture of the DRX 3960A, the

IC cannot react immediately to an I2C request. The

typical

response

time

about

0.3 ms.

the

DRX 3960A cannot accept another complete byte of

data until it has performed some other function (for

example, servicing an internal interrupt), it will hold the

clock line low to force the transmitter into a wait state.

The maximum wait period during normal operation

mode is less than 1 ms.

Table 4–1: I2C Bus Device Addresses

ADR_SEL

Low

High

Left Open

Mode

Write

Read

Write

Read

Write

Read

Device address

82hex

83hex

86hex

87hex

8Ahex

8Bhex

Table 4–2: I2C Bus Subaddresses

Name

Binary Value

Hex Value

Mode

Function

CONTROL

0000 0000

Read/Write

Write

: Software reset of DRX

Read

: Hardware error status of DRX

PORT

0000 0011

Write

output port address

WR_DRX

0001 0000

Write

write address

RD_DRX

0001 0001

Write

read address

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