AD5241 datasheet(3/16 Pages) AD

3 / 16 page

REV. B

–3–

AD5241/AD5242

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

INTERFACE TIMING CHARACTERISTICS (Applies to all parts.

5, 9)

SCL Clock Frequency

fSCL

400

kHz

tBUF Bus Free Time between

1.3

µs

STOP and START

tHD; STA Hold Time (Repeated START)

After this period, the first clock

600

pulse is generated.

tLOW Low Period of SCL Clock

1.3

µs

tHIGH High Period of SCL Clock

0.6

µs

tSU; STA Setup Time for Repeated

START Condition

600

tHD; DAT Data Hold Time

900

tSU; DAT Data Setup Time

100

tR Rise Time of Both

300

SDA and SCL Signals

tF Fall Time of Both SDA and SCL Signals

300

tSU; STO Setup Time for STOP Condition

t10

NOTES

1Typicals represent average readings at 25

°C, V

DD = 5 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-

tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.

3INL and DNL are measured at V

W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.

DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 10.

4Resistor terminals A, B, W have no limitations on polarity with respect to each other.

5Guaranteed by design and not subject to production test.

DISS is calculated from (IDD

× V

DD). CMOS logic level inputs result in minimum power dissipation.

7Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-

width. The highest R value results in the minimum overall power consumption.

8All dynamic characteristics use V

DD = 5 V.

9See timing diagram for location of measured values.

Specifications subject to change without notice.

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