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WM8980 датащи(PDF) 65 Page - Wolfson Microelectronics plc |
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WM8980 датащи(HTML) 65 Page - Wolfson Microelectronics plc |
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65 / 81 page ![]() Product Preview WM8980 w PP Rev 1.6 January 2005 65 Similar to the output enables, VMID, which can be driven out of OUT3 can be configured to be on/off depending on the jack detection input polarity using the VMID_EN_0 and VMID_EN_1 bits. The jack detection enables work as follows: All OUT_EN signals have an AND function performed with their normal enable signals (in Table 40). When an output is normally enabled at per Table 40, the selected jack detection enable (controlled by selected jack detection pin polarity) is set 0, it will turn the output off. If the normal enable signal is already OFF (0), the jack detection signal will have no effect due on the AND function. During jack detection if the user desires an output to be un-changed whether the jack is in or not, both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000. The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should set to 0 for all JD_EN0 or JD_EN1 settings. If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs to be controlled as normal via the normal output enables found in Table 40. Similarly the VMID_EN signal defaults to 0 allowing the VMID driver to be controlled via the normal enable bit. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 5:4 JD_SEL 00 Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = GPIO4 6 JD_EN 0 Jack Detection Enable 0=disabled 1=enabled R9 GPIO Control 8:7 JD_VMID 00 [7] VMID_EN_0 [8] VMID_EN_1 3:0 JD_EN0 0 Output enabled when selected jack detection input is logic 0. [0]= OUT1_EN_0 [1]= OUT2_EN_0 [2]= OUT3_EN_0 [3]= OUT4_EN_0 R13 GPW Control 7:4 JD_EN1 0 Output enabled when selected jack detection input is logic 1 [4]= OUT1_EN_1 [5]= OUT2_EN_1 [6]= OUT3_EN_1 [7]= OUT4_EN_1 Table 54 Jack Detect Register Control Bits |
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