Production Data

WM9709

w

PD Rev 1.3 February 2003

7

SDATAOUT

SDATAIN,

BITCLK

t

setup2rst

RESETB

t

off

Hi-Z

Figure 4 ATE Test Mode Timing

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Setup to trailing edge of RESETB

(also applies to SYNC)

15.0

-

-

nS

Rising edge of RESETB to Hi-Z

delay

-

-

25.0

nS

Notes:

1.

All WM9709 signals are normally low through the trailing edge of RESETB. Bringing

SDATAOUT high for the trailing edge of RESETB causes WM9709’s AC-link outputs to go high

impedance, which is suitable for ATE in circuit testing.

2.

A vendor specific internal test mode can be entered by bringing SYNC high for the trailing edge

of RESETB. This mode has no effect on WM9709 AC-link output signal levels.

3.

Once either of the two test modes have been entered, WM9709 must be issued another

RESETB with all AC-link signals low to return to the normal operating mode.

SIGNAL RISE AND FALL TIMES

BITCLK

SYNC

SDATAIN

SDATAOUT

trise

CLK

tfall

CLK

trise

SYNC

tfall

SYNC

trise

DIN

tfall

DIN

trise

DOUT

tfall

DOUT

Figure 5 Signal Rise and Fall Times (50pF external load)