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WM9709 датащи(PDF) 5 Page - Wolfson Microelectronics plc |
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WM9709 датащи(HTML) 5 Page - Wolfson Microelectronics plc |
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5 / 18 page ![]() Production Data WM9709 w PD Rev 1.3 February 2003 5 Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. SNR measured with A-weight filter is typically 2dB better than with CCIR2k filter, or 20kHz low pass filter. TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. 3. Dynamic range (dB) - DNR is a measure of the ratio between the largest and smallest usable signals. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= 42dB, DNR= 102dB). 4. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. SERIAL INTERFACE TIMINGS Test Conditions: AVDD = 5V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = 25 oC, unless otherwise stated. All measurements are taken at 10% to 90% VDD, unless otherwise stated. All the following timing information is guaranteed by design, but not tested in production. COLD RESET RESETB BITCLK t RST_LOW t RST2CLK Figure 1 Cold Reset Timing PARAMETER SYMBOL MIN TYP MAX UNIT RESETB active low pulse width tRST_LOW 1.0 µs RESETB inactive to BITCLK startup delay tRST2CLK 162.8 ns WARM RESET Not supported by WM9709 |
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