WM8775

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PP Rev 1.8, June 2004

22

In addition a zero cross detect circuit is provided for the input PGA. When ZCLA/ZCRA is set with a

write, the gain will update only when the input signal approaches zero (midrail). This minimises

audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which

will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of

12.288MHz). The timeout clock may be disabled by setting TOD.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

0000111

Timeout Clock Disable

3

TOD

0

Analogue PGA Zero cross detect

timeout disable

0 : Timeout enabled

1: Timeout disabled

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

LAG[7:0]

11001111

(0dB)

Attenuation data for Left channel ADC gain in 0.5dB steps. See

Table 11.

R14(0Eh)

0001110

Attenuation

ADCL

8

ZCLA

0

Left channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

7:0

RAG[7:0]

11001111

(0dB)

Attenuation data for right channel ADC gain in 0.5dB steps. See

Table 11.

R15(0Fh)

0001111

Attenuation

ADCR

8

ZCRA

0

Right channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

R21(15h)

0010101

ADC Input Mux

8

LRBOTH

0

Right channel input PGA controlled by left channel register

0 : Right channel uses RAG.

1 : Right channel uses LAG.

7

MUTELA

0

Mute for left channel ADC

0: Normal Operation

1: Mute ADC left

R21(15h)

0010101

ADC Mute

6

MUTERA

0

Mute for right channel ADC

0: Normal operation

1: Mute ADC right

ADC HIGHPASS FILTER DISABLE

The ADC digital filters contain a digital high pass filter. This defaults to enabled and can be disabled

using software control bit ADCHPD.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R11(0Bh)

0001011

ADC Control

8

ADCHPD

0

ADC High pass filter disable:

0: High pass filter enabled

1: High pass filter disabled