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WM8775EDS/R датащи(PDF) 13 Page - Wolfson Microelectronics plc

номер детали WM8775EDS/R
подробное описание детали  24 BIT 96 KHZ ADC WITH 4 CHANNEL I/P MULTIPLEXER
PDF  36 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8775EDS/R датащи(HTML) 13 Page - Wolfson Microelectronics plc

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WM8775
w
PP Rev 1.8, June 2004
13
In Master mode BCLK and ADCLRC are generated by the WM8775. The frequency of ADCLRC is
set by setting the required ratio of MCLK to ADCLRC using the ADCRATE control bit (Table 7).
ADCRATE[2:0]
MCLK:ADCLRC RATIO
010
256fs
011
384fs
100
512fs
101
768fs
Table 7 Master Mode MCLK:ADCLRC Ratio Select
Table 8 shows the settings for ADCRATE for common sample rates and MCLK frequencies.
System Clock Frequency (MHz)
256fs
384fs
512fs
768fs
SAMPLING
RATE
(ADCLRC)
ADCRATE
=010
ADCRATE
=011
ADCRATE
=100
ADCRATE
=101
32kHz
8.192
12.288
16.384
24.576
44.1kHz
11.2896
16.9340
22.5792
33.8688
48kHz
12.288
18.432
24.576
36.864
96kHz
24.576
36.864
Unavailable
Unavailable
Table 8 Master Mode ADCLRC Frequency Selection
BCLK is also generated by the WM8775. The frequency of BCLK depends on the mode of operation.
If using 256, 384, 512 or 768fs (ADCRATE=010, 011,100 or 101) BCLK = MCLK/4. However if DSP
mode is selected as the audio interface mode then BCLK=MCLK.
POWERDOWN MODES
The WM8775 has powerdown control bits allowing specific parts of the WM8775 to be powered off
when not being used. The 4-channel input source selector and input buffer may be powered down
using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN4L/R)
are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input
PGAs. Setting AINPD and ADCPD will powerdown everything except the references VMIDADC and
ADCREFP. These may be powered down by setting PDWN. Setting PDWN will override all other
powerdown control bits. It is recommended that the 4-channel input mux and buffer AINPD and
ADCPD are powered down before setting PDWN. The default is for all powerdown bits to be 0 i.e.
enabled.



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