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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RT6908 датащи(PDF) 13 Page - Richtek Technology Corporation |
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RT6908 датащи(HTML) 13 Page - Richtek Technology Corporation |
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13 / 22 page  RT6908 13 DS6908-01 March 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. © Application Information I2C Command Single I2C Register Write Protocol Single I 2C Register Read Protocol Multiple I2C Register Write Protocol Multiple I2C Register Read Protocol Register Map Address Name Description Default Value Resolution Range 00h AVDD [5 : 0] Boost 15.6V (1Dh) 0.1V 12.7V to 19V (00h to 3Fh) 01h VGH [4 : 0] VGH 35.5V (16h) 0.5V 24.5V to 40V (00h to 1Fh) 02h VGL [5 : 0] VGL −6V (2Ah) −0.1V −1.8V to −8.1V (00h to 3Fh) 03h VIO [3 : 0] VIO adjustment 0% (07h) 1% −7% to 7% (00h to 0Eh) 04h VCORE [3 : 0] VCORE adjustment 0% (07h) 1% −7% to 7% (00h to 0Eh) 05h DLY1 [3 : 0] VGL Delay Time 200ms (01h) DLYR1 0 to 15 x DLYR1 (00h to 0Fh) 06h DLY2 [3 : 0] AVDD Delay Time 400ms (02h) DLYR2 0 to 15 x DLYR2 (00h to 0Fh) 07h DLY3 [3 : 0] VGH Delay Time 10ms (01h) DLYR3 0 to 15 x DLYR3 (00h to 0Fh) 08h DLYR1 [1 : 0] DLY1 Resolution 200ms (02h) 1ms, 10ms, 200ms 09h DLYR2 [1 : 0] DLY2 Resolution 200ms (02h) 1ms, 10ms, 200ms 0Ah DLYR3 [1 : 0] DLY3 Resolution 10ms (01h) 1ms, 10ms, 200ms 0Bh SS [3 : 0] AVDD Soft-Start Time 2ms (02h) 1ms 0ms to 15ms (00h to 0Fh) 0Ch ILIMGD [3 : 0] Isolation Switch Current Limit Disable (00h) 50mV Disable, 100mV to 800mV (00h to 0Fh) FFh CTRL [7 : 0] ’’55h’’ Start Power On Sequence 00h Slave Address 1 1 0 1 0 0 0 Register Address D7 D6 D5 D4 D3 D2 D1 D0 Slave ACK Stop Slave ACK Slave ACK A0 Stop Slave Address 1 1 0 1 0 0 0 Register Address Slave ACK Slave ACK Stop Slave ACK A0 Master NACK Stop Slave Address Re- Start 1 1 0 1 0 0 1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Slave Address 7 6 5 4 3 2 1 0 = LSB 1 1 0 1 0 0 A0 R/W Slave Address 1 1 0 1 0 0 0 Register Address D7 D6 D5 D4 D3 D2 D1 D0 Slave ACK Slave ACK Slave ACK A0 Stop D7 D6 D5 D4 D3 D2 D1 D0 Slave ACK D7 D6 D5 D4 D3 D2 D1 D0 Slave ACK Stop Slave Address 1 1 0 1 0 0 0 Register Address Slave ACK Slave ACK Stop Slave ACK A0 Master NACK Stop Slave Address Re- Start 1 1 0 1 0 0 1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Master ACK D7 D6 D5 D4 D3 D2 D1 D0 |
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