DLP2000 datasheet(9/40 Pages) TI1

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DLP2000

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DLPS078 – JULY 2017

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(1)

The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of

maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the

DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the

window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling

outside the window aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.5 Thermal Information

THERMAL METRIC(1)

DLP2000

UNIT

FQC (LGA)

42 PINS

Thermal resistance active area to test point 1 (TP1) (1)

°C/W

(1)

Includes LVCMOS pins only.

(2)

LVCMOS input pins do not have Pull-up or Pull-down configurations.

(3)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than 8.75 V.

(4)

When DRC_OEZ = High, the internal reset drivers are tri-stated and IBIAS standby current is 3.8 mA.

(5)

Nominal values are measured with VCC = 1.8 V, VOFFSET = 8.5 V, VBIAS = 16 V, and VRESET = –10 V.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High level output voltage

VCC = 1.65 V

IOH = –2 mA

1.20

VOL

Low level output voltage

VCC = 1.95 V

IOL = –2 mA

0.45

IIL

Low level input current (1)(2)

VCC = 1.95 V

VI = 0 V

IIH

High level input current (1)(2)

VCC = 1.95 V

VI = 1.95 V

CURRENT

ICC

Current at VCC = 1.95 V

DCLK Frequency = 77 MHz

IOFFSET

Current at VOFFSET = 8.75 V

(3)

1.5

IBIAS

Current at VBIAS = 16.5 V

(3) (4)

3 Global Resets within time period = 200 µs

1.3

IRESET

Current at VRESET = –10.5 V

3 Global Resets within time period = 200 µs

1.2

POWER

PCC

Power at VCC = 1.95 V

(5)

DCLK Frequency = 77 MHz

POFFSET

Power at VOFFSET = 8.75 V

(5)

PBIAS

Power at VBIAS = 16.5 V

(5)

3 Global Resets within time period = 200 µs

PRESET

Power at VRESET = –10.5 V

(5)

3 Global Resets within time period = 200 µs

PTOTAL

Supply power dissipation Total

107

CAPACITANCE

CIN

Input Capacitance

f = 1 MHz

COUT

Output Capacitance

f = 1 MHz

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