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RT9428WSC датащи(PDF) 11 Page - Richtek Technology Corporation

номер детали RT9428WSC
подробное описание детали  Host-Side Single Cell Lithium Battery Gauge
PDF  14 Pages
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производитель  RICHTEK [Richtek Technology Corporation]
домашняя страница  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT9428WSC датащи(HTML) 11 Page - Richtek Technology Corporation

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RT9428
11
DS9428-01
October 2014
www.richtek.com
©
Copyright
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
Register
Bit
Description
0x0A
7 : 6
Reserved
5
SC
4
SL
3 : 1
Reserved
0
RI
Figure 5. Status Register
Figure 4. OCV Register
Figure 6. RT9428 Application Example with Alert Interrupt
VBAT
RT9428
QS
TEST
SDA
GND
VDD
SCL
R2
150
R3
4.7k
System
Processor
SDA
SCL
R1
1k
C1
1µF
C2
10nF
Protection IC
(Li+/Polymer)
System GND
+
Battery PACK
Pack+
Pack-
ALERT
IRQ
IO Power
PMIC_VBAT
PMIC_GND
A byte of data consists of 8 bits ordered MSB first and
the LSB followed by the Acknowledge bit.
The RT9428 address is 0110110 (6Ch) and is a receive
only (slave) device. The second word selects the register
to which the data will be written. The third word contains
data to write to the selected register.
Table 4 applies to the transaction formats.
MSB-Address 0Eh
MSB
2
11
LSB MSB
LSB
LSB-Address 0Fh
0
0
0
0
2
9
2
10
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
0 : Bits Always Read Logic 0
Unit : 1.25mV
Figure 7. I
2C Timing Diagram
Read Protocol
Write Protocol
S
SAddr
W A
CAddr
A
Data0
A
Data1
A P
S
SAddr
W A
CAddr
A
SAddr
R
Data0
A
Sr
A
Data1
N P
Figure 6 presents a single cell battery-powered system
application. The RT9428 is used on system side and direct
powered from the battery.
The RC filter saves the noise for IC power supply and
voltage measurement on VBAT pin.
To reduce the I-R drop effect, make the connection of VBAT
as close as possible to the battery pack.
The ALERT pin provides a battery low interrupt signal to
system processor when capacity low is detected.
The QS pin is unused in this configuration, so it needs to
be tied to GND.
I
2C Bus Interface
Figure 7 shows the timing diagram of the I
2C interface.
The RT9428 communicates with a host (master) by using
the standard I
2C 2-wire interface.After the START condition,
the I
2C master sends 8-bit data, consisting of 7-bit slave
address and a following data direction bit (R/W).



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