RT8092BCGWSC datasheet(23/27 Pages) RICHTEK

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RT8092

DS8092-03 January 2017

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Figure 8. Derating Curve of Maximum Power Dissipation

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJAis the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

WL-CSP-15B 1.2x2 (BSC) package, the thermal

resistance,

θJA, is 51.9°C/W on a standard JEDEC 51-7

four-layer thermal test board. For WQFN-14L 3.5x3.5

package, the thermal resistance,

θJA, is 30°C/W on a

standard JEDEC 51-7 four-layer thermal test board. The

maximum power dissipation at TA = 25

°C can be calculated

by the following formula :

PD(MAX) = (125

°C − 25°C) / (51.9°C/W) = 1.92W for

WL-CSP-15B 1.2x2 package

PD(MAX) = (125

°C − 25°C) / (30°C/W) = 3.33W for

WQFN-14L 3.5x3.5 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curve in Figure 8 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

WQFN-14L 3.5x3.5

WL-CSP-15B 1.2x2

Layout Consideration

For the best performance of the RT8092, the following

PCB layout guidelines must be strictly followed.



Place the input and output capacitors as close as

possible to the input and output pins respectively for

good filtering.



Keep the main power traces as wide and short as

possible.



The switching node area connected to LX and inductor

should be minimized for lower EMI.



Place the feedback components as close as possible

to the VOUT pin and keep these components away from

the noisy devices.

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