IR3092

Page 2 of 37

06/25/04

PIN DESCRIPTION

PIN# PIN SYMBOL PIN DESCRIPTION

1

VID3

Inputs to VID D to A Converter

2

VID4

Inputs to VID D to A Converter

3

ROSC

Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents

4

VOSNS-

Remote Sense Input. Connect to ground at the Load.

5

OCSET

Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current

source.

6

VDAC

Regulated voltage programmed by the VID inputs. Current Sensing and Over Current Protection are referenced

to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate.

7

VDRP

Buffered IIN signal. Connect an external RC network to FB to program converter output impedance

8

FB

Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an

external resistor connected to the converter output voltage at the load and an internal current source. Bias

current is a function of ROSC. Also OVPsense.

9

EAOUT

Output of the Error Amplifier

10

SS/DEL

Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to LGND to

program the timing.

11

SCOMP

Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s

bandwidth. Phase 2 is forced to match phase 1’s current.

12

N/C

No Connect.

13

LGND

Local Ground and IC substrate connection

14

SETBIAS

External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC.

15

VCC

Power for internal circuitry and source for BIASOUT regulator

16-17

N/C

No Connect.

18

BIASOUT

150mA open-looped regulated voltage set by SETBIAS for GATE drive bias.

19

PWRGD

Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up.

20

CSINP2

Non-inverting input to the Phase 2 Current Sense Amplifier.

21

N/C

No Connect.

22

VID_SEL

Ground Selects VR10 VID, Float Selects OPTERON VID, VCC Selects ATHLON VID

23-27

N/C

No Connect.

28

VCCH2

Power for Phase 2 High-Side Gate Driver

29

GATEH2

Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator.

30

PGND2

Return for Phase 2 Gate Drivers

31

GATEL2

Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator.

32

5VUVL

Can be used to monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under

voltage condition initiates Soft Start.

33

VCCL

Power for Phase 1 and 2 Low-Side Gate Drivers.

34

GATEL1

Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator.

35

PGND1

Return for Phase 1 Gate Drivers

36

GATEH1

Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator.

37

VCCH1

Power for Phase 1 High-Side Gate Driver

38

NC

Not connected

39

CSINM1

Inverting input to the Phase 1Current Sense Amplifier.

40

CSINP1

Non-inverting input to the Current Sense Amplifier.

41

OVP

Output that drives high during an Over-Voltage condition.

42

ENABLE

Enable Input. A logic low applied to this pin puts the IC into Fault mode.

43-44

N/C

No Connect.

45

VID5

Inputs to VID D to A Converter

46

VID0

Inputs to VID D to A Converter

47

VID1

Inputs to VID D to A Converter

48

VID2

Inputs to VID D to A Converter