IR3092

Page 21 of 37

06/25/04

Adaptive Voltage Positioning

Adaptive voltage positioning is needed to reduce output voltage deviations during load transients and power dissipation of

the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in Figure 9. Resistor

selected to program the desired amount of fixed offset voltage below the DAC voltage.

The voltage at the VDRP pin is an average of both phase Current Sense Amplifiers and represents the sum of the VDAC

voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor.

The Error Amplifier forces the voltage on the FB pin to equal VDAC through the power supply loop therefore the current

voltage reduction proportional to an increase in load current. The droop impedance or output impedance of the converter

of the VDAC voltage.

AMD specifies the acceptable power supply regulation window as ±50mV around their specified VID tables. VR10.X

specifies the VID table voltages as the absolute maximum power supply voltage. In order to have all three DAC options,

the OPTERON and ATHLON DAC output voltages are pre-positioned 50mV higher than listed in AMD specs. During

testing, a series resistor is placed between EAOUT and FB to cancel the additional 50mV out of the DAC. The FB bias

current, equal to IROSC, develops the 50mV cancellation voltage. Trimming the VDAC voltage by monitoring V(EAOUT)

with this 50mV cancellation resistor in circuit also trims out errors in the FB bias current.

The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can be

retrieved by subtracting the VDAC voltage from the VDRP voltage.

CSINM3

CSINM2

- V(CSavg) +

VDRP BUFFER

IROSC

+

VPOSITIONING

-

IDRP

RDRP

CDAC

ERROR AMPLIFIER

RCOMP

VDAC

CCOMP

RDAC

RFB

IROSC

VDAC

VDRP

VOSNS-

FB

VOUT SENSE+

EAOUT

VOUT SENSE-

CSINP2

VDAC

-

+

X24.5

CSINP3

VDAC

-

+

X24.5

Figure 9 - Adaptive voltage positioning