HCPL0738 datasheet(6/8 Pages) HP

6 / 8 page

Propagation Delay, Pulse-Width

Distortion, and Propagation Delay

Skew

Propagation delay is a figure of

merit which describes how

quickly a logic signal propagates

through a system. The propaga-

tion delay from low to high (t

PLH)

is the amount of time required for

an input signal to propagate to

the output, causing the output to

change from low to high.

Similarly, the propagation delay

from high to low (t

PHL) is the

amount of time required for the

Figure 6. Recommended printed circuit board layout.

Application Information

Bypassing and PC Board Layout

The HCPL-0738 optocoupler is

extremely easy to use. No exter-

nal interface circuitry is required

because the HCPL-0738 uses

high-speed CMOS IC technology

allowing CMOS logic to be con-

nected directly to the inputs and

outputs.

input signal to propagate to the

output, causing the output to

change from high to low (see

Figure 7).

Pulse-width distortion (PWD)

results when t

PLH and tPHL differ

in value. PWD is defined as the

difference between t

PLH and tPHL

and often determines the maxi-

mum data rate capability of a

transmission system. PWD can

be expressed in percent by

dividing the PWD (in ns) by the

minimum pulse width (in ns)

being transmitted. Typically,

PWD on the order of 20-30% of

the minimum pulse width is

tolerable; the exact figure de-

pends on the particular applica-

tion (RS232, RS422, T-1, etc.).

Propagation delay skew, t

PSK, is

an important parameter to con-

sider in parallel data applications

where synchronization of signals

on parallel data lines is a con-

cern. If the parallel data is being

sent through a group of

optocouplers, differences in

propagation delays will cause the

data to arrive at the outputs of

As shown in Figure 6, the only

external component required for

proper operation is the bypass

capacitor. Capacitor values

should be between 0.01

µF and

0.1

µF. For each capacitor, the

total lead length between both

ends of the capacitor and the

power-supply pins should not

exceed 20 mm.

GND 2

VDD

GND 1

VO 2

VO 1

VI1

GND 1

VI2

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