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WM8255 датащи(PDF) 41 Page - Cirrus Logic |
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WM8255 датащи(HTML) 41 Page - Cirrus Logic |
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41 / 49 page ![]() WM8255 Production Data w PD, Rev 4.7, August 2013 41 Address <a5:a0> Description Def (hex) RW BIT b7 b6 b5 b4 b3 b2 b1 b0 101011 PGA Gain (RGB) 00 W PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] 101100 Setup Reg 19 10 RW LEDSTART [5] LEDSTOPG [6] LEDSTOPG [5] LEDSTOPG [4] LEDSTOPG [3] LEDSTOPG [2] LEDSTOPG [1] LEDSTOPG [0] 101101 Setup Reg 20 10 RW LEDSTART [6] LEDSTOPB [6] LEDSTOPB [5] LEDSTOPB [4] LEDSTOPB [3] LEDSTOPB [2] LEDSTOPB [1] LEDSTOPB [0] 101110 Setup Reg 21 00 RW ILIMITFLAG ILIMITDEC INITBLANK [8] INITBLANK [7] INITBLANK [6] INITBLANK [5] INITBLANK [4] INITBLANK [3] 101111 LED Software Reset 00 W LED RGB Flags 00 R LEDRFLAG LEDGFLAG LEDBFLAG Table 8 Register Map EXTENDED PAGE REGISTERS Address <a5:a0> Description Def (hex) RW BIT b7 b6 b5 b4 b3 b2 b1 b0 100100 LED Control 0 0 LED_TEST CTRL[3] LED_TEST CTRL[2] LED_TEST CTRL[1] LED_TEST CTRL[0] 0 0 100111 Revision Number REV_NUM [6] REV_NUM [5] REV_NUM [4] REV_NUM [3] REV_NUM [2] REV_NUM [1] REV_NUM [0] X Table 9 Extended Page Registers Note: To access the Extended Page Registers the TREG_OPEN bit must be set to ‘1’ in Setup Reg 1. This bit must then be set to ‘0’ once access is complete. Please refer to Pages 23 and 38 for details on when to access these registers. REGISTER MAP DESCRIPTION The following table describes the function of each of the control bits shown in Table 8. REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION Setup Register 1 0 EN 1 0 = complete power down, 1 = fully active. 1 CDS 1 Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. 2 Reserved 0 Must be set to zero 3 VSMPDET 0 0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronization pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. 5:4 PGAFS[1:0] 00 Offsets PGA output to optimize the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output (use for bipolar video) 01 = Zero output 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video) 6 MODE3 0 Required when operating in MODE3: 0 = other modes, 1 = MODE3. 7 TREG_OPEN 0 Enables the extended page register access |
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