WM8255 datasheet(16/49 Pages) CIRRUS

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Production Data

WM8255

PD, Rev 4.7, August 2013

ADC INPUT BLACK LEVEL ADJUST

The output from the PGA should be offset to match the full-scale range of the ADC (VFS = 2.0V). For

negative-going input video signals, a black level (zero differential) output from the PGA should be

offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input

signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.

Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential

input voltage gives mid-range ADC output).

OVERALL SIGNAL FLOW SUMMARY

Figure 10 represents the processing of the video signal through the WM8255.

VRESET

VVRLC

CDS = 1

CDS = 0

VRLCEXT=1

250mV*(DAC[7:0]-127.5)/127.5

analog

See parametrics for

DAC voltages.

OP pins

digital

ADC BLOCK

PGA

BLOCK

OFFSET DAC

BLOCK

INPUT

SAMPLING

BLOCK

CDS, VRLCEXT, RLCV[3:0], DAC[7:0],

PGA[7:0], PGAFS[1:0] and INVOP are set

by programming internal control registers.

CDS=1 for CDS, 0 for non-CDS

VIN is VINP

VRESET is VIN sampled during reset clamp

VRLC is voltage applied to VRLC/VBIAS pin

VIN

x (65535/VFS)

if PGAFS[1:0]=11

+65535 if PGAFS[1:0]=10

+32767 if PGAFS[1:0]=0x

PGA gain

A= 0.78+PGA[7:0]x7.57/255

OUTPUT

INVERT

BLOCK

D2 = D1 if INVOP = 0

D2 = 65535-D1 if INVOP = 1

Offset

DAC

RLC

DAC

VRLCEXT=0

Figure 10 Overall Signal Flow

The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the

difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the

difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally

set via the RLC DAC.

The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the

black level of the input signal towards 0V, producing V2.

The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,

outputting voltage V3.

The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.

The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.

CALCULATING OUTPUT FOR ANY GIVEN INPUT

The following equations describe the processing of the video and reset level signals through

the WM8255.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the

input video.

VIN - VRESET

Eqn. 1

If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted

instead.

VIN - VVRLC

Eqn. 2

If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.

If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.

VVRLC

(VRLCSTEP  RLCV[3:0]) + VRLCBOT

Eqn. 3

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