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WM8233 датащи(PDF) 31 Page - Cirrus Logic

номер детали WM8233
подробное описание детали  210MSPS 6-Channel AFE with Sensor
PDF  146 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8233 датащи(HTML) 31 Page - Cirrus Logic

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WM8233
Rev 4.7
31
CMOS OUTPUT MODE
IN1
IN2
IN3
IN4
IN5
IN6
MCLK x1
MCLK x6 (OCLK)
OP9
OP8
OP7
OP6
OP5
OP4
IN1
IN2
IN3
IN4
IN5
IN6
OP3
OP2
OP1
OP0
MCLK x6 (OC1)
A
IN1
IN2
IN3
IN4
MCLK x2
(ADCLK)
ADC1
ADC2
IN5
IN6
ADC3
A
OP9
IN1[9]
IN2[9]
IN3[9]
IN4[9]
IN5[9]
IN6[9]
OP8
IN1[8]
IN2[8]
IN3[8]
IN4[8]
IN5[8]
IN6[8]
OP7
IN1[7]
IN2[7]
IN3[7]
IN4[7]
IN5[7]
IN6[7]
OP6
IN1[6]
IN2[6]
IN3[6]
IN4[6]
IN5[6]
IN6[6]
OP5
IN1[5]
IN2[5]
IN3[5]
IN4[5]
IN5[5]
IN6[5]
OP4
IN1[4]
IN2[4]
IN3[4]
IN4[4]
IN5[4]
IN6[4]
OP3
IN1[3]
IN2[3]
IN3[3]
IN4[3]
IN5[3]
IN6[3]
OP2
IN1[2]
IN2[2]
IN3[2]
IN4[2]
IN5[2]
IN6[2]
OP1
IN1[1]
IN2[1]
IN3[1]
IN4[1]
IN5[1]
IN6[1]
OP0
IN1[0]
IN2[0]
IN3[0]
IN4[0]
IN5[0]
IN6[0]
Table 10 10-bit CMOS Output Format
CLOCK TIMING CONFIGURATION
The RSMP signal, VSMP signal and clock output from CLK pin are generated internally by 60 tap DLL
circuit. The rising and falling timing of each clock is set by DLL tap setting. The following setting and
timing chart shows example configuration for RSMP, VSMP and CLK1.
RSMP: 0x82(RSMP_RISE)=0x07(dec7), 0x83(RSMP_FALL)=0x10(dec16)
VSMP: 0x84(VSMP_RISE)=0x1C(dec28), 0x85(VSMP_FALL=0x29(dec41)
CLK1: 0x87(CLK1_RISE)=0x39(dec57), 0x88(CLK1_FALL)=0x0B(dec11)



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