WM8533 datasheet(16/41 Pages) CIRRUS

16 / 41 page

WM8533

Production Data

PD, July 2012, Rev 4.0

2C CONTROL MODE

In I

2C mode, the WM8533 is a slave device on the control interface; SCLK is a clock input, while SDA

is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the

same interface, the WM8533 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high.

An external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised

by the master.

In order to allow many devices to share a single I

2C control bus, every device on the bus has a

unique 8-bit device ID (this is not the same as the 8-bit address of each register in the WM8533).

The device ID is determined by the logic level on the CS

¯¯ pin as shown in Table 7. The LSB of the

device ID is the R/W

¯¯ bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.

¯¯

DEVICE ID

0011 0100 (34h)

0011 0110 (36h)

Table 7 Control Interface Device ID Selection

The WM8533 operates as an I

2C slave device only. The controller indicates the start of data transfer

with a high to low transition on SDA while SCLK remains high. This indicates that a device ID,

next eight bits on SDA (8-bit device ID, including Read/Write bit, MSB first). If the device ID received

matches the device address of the WM8533, then the WM8533 responds by pulling SDA low on the

next clock pulse (ACK). If the device ID is not recognised or the R/W

¯¯ bit is set incorrectly, the

WM8533 returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM8533, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDA while

SCLK remains high. After receiving a complete address and data sequence the WM8533 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns

to the idle condition.

The WM8533 supports the following read and write operations:



Single write



Single read

The sequence of signals associated with a single register write operation is illustrated in Figure 8.

Figure 8 Control Interface I

2C Register Write

The sequence of signals associated with a single register read operation is illustrated in Figure 9.

Figure 9 Control Interface I

2C Register Read

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