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WM8533 датащи(PDF) 11 Page - Cirrus Logic |
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WM8533 датащи(HTML) 11 Page - Cirrus Logic |
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11 / 41 page ![]() Production Data WM8533 w PD, July 2012, Rev 4.0 11 CONTROL INTERFACE TIMING – I2C MODE I 2C mode is selected by driving the CIFMODE pin low. Figure 4 Control Interface Timing – I 2C Control Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 400 kHz SCLK Low Pulse-Width t1 100 ns SCLK High Pulse-Width t2 100 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 ns SDA, SCLK Rise Time (see Note) t6 300 ns SDA, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t8 600 ns Data Hold Time t9 900 ns Pulse width of spikes that will be suppressed 2 8 ns Table 3 Control Interface Timing – I 2C Control Mode Note: When SCLK frequency ≤ 100kHz, the maximum rise time for SDA and SCLK is increased to 1000ns. |
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