CS53L30 datasheet(6/67 Pages) CIRRUS

6 / 67 page

DS992F2

CS53L30

1.3 Pin Descriptions

MIC_BIAS_FILT

I Microphone Bias Voltage Filter. Filter

connection for the internal quiescent

voltage used for the MICx_BIAS outputs.

——

—

FILT+

O Positive Reference Filter. Positive

reference voltage filter for internal

sampling circuits.

——

—

MIC1_BIAS

MIC2_BIAS

MIC3_BIAS

MIC4_BIAS

O Microphone Bias Voltage. Low-noise

bias supply for an external mic.

——

—

Hi-Z

INT

—17

O Interrupt. Outgoing interrupt signal

generated upon registering an error

(fault).

—CMOS

open-drain

output

—Hi-Z

RESET

I Reset. The device enters a low power

mode when this pin is driven low.

—

Hysteresis

on CMOS

input

—

SYNC

I/O Multidevice Synchronization Signal.

Synchronization output when SYNC_EN

is set, otherwise it is a synchronization

input. Defaults to input.

Weak

pulldown

CMOS

output

Hysteresis

on CMOS

input

Hi-Z

SCL

I Serial Control Port Clock. Serial clock

for the I2C port.

—

Hysteresis

on CMOS

input

—

SDA

I/O Serial Control Data. Bidirectional data

pin for the I2C port.

—CMOS

open-drain

output

Hysteresis

on CMOS

input

—

MCLK

I Master Clock. Clock source for device’s

core.

Weak

pulldown

—

Hysteresis

on CMOS

input

—

ASP_SCLK

I/O Audio Serial Clock. Audio bit clock. Input

in Slave Mode, output in Master Mode.

Weak

pulldown

CMOS

output

Hysteresis

on CMOS

input

Hi-Z

ASP_LRCK/

FSYNC

I/O Audio Left/Right Clock/Frame SYNC.

Identifies the start of each serialized PCM

data word and indicates the active

channel on each serial PCM audio data

line. Input in Slave Mode, output in Master

Mode.

Weak

pulldown

CMOS

output

Hysteresis

on CMOS

input

Hi-Z

ASP_SDOUT1

O Audio Data Output. Output for the two’s

complement serial PCM data. Channels 1

and 2 are output in I2S Mode, while all four

channels of data are output on this single

pin in TDM Mode.

Weak

pulldown

Tristateable

CMOS

output

—Hi-Z

ASP_SDOUT2/

AD0

I/O Audio Data Output/Address Select.

Output for the two’s-complement serial

PCM data. Channels 3 and 4 are output in

I2S Mode. Along with DMIC2_SCLK/AD1,

immediately sets the I2C address when

RESET is deasserted. Default is 0.

Weak

pulldown

Tristateable

CMOS

output

—Hi-Z

DMIC1_SCLK

O Digital MIC Interface 1 Serial Clock.

High speed clock output to the digital

mics.

Weak

pulldown

CMOS

output

—Hi-Z

Table 1-1. Pin Descriptions (Cont.)

Name

Ball

Power

Supply

I/O

Description

Internal

Connection

Driver

Receiver

State at

Reset

Filter pins

Analog Outputs

Digital I/O

CS53L30 датащи(PDF) 6 Page - Cirrus Logic

CS53L30 датащи(HTML) 6 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

датащи скачать

ссылки URL