HT56RB688_13 datasheet(97/164 Pages) HOLTEK

97 / 164 page

SIM the interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts,

however only the MF0F or MF1F interrupt request flag will be reset. As the SIM request flag known as

SIM0F or SIM1F will not be automatically reset, it has to be cleared by the application program.

Multi-function Interrupt

Two additional interrupts known as the Multi-function 0 interrupt and Multi-function 1 interrupt are

provided. Unlike the other interrupts, the interrupt has no independent source, but rather is formed from

several other existing interrupt sources. The Multi-function 0 interrupt contains the SIM0 interrupt, Time

Base interrupt, Real Time Clock interrupt, External Peripheral interrupt while the Multi-function 1

interrupt contains the SIM1 interrupt, Timer 2 overflow interrupt and Timer 3 overflow interrupt.

For a Multi-function interrupt to occur, the global interrupt enable bit, EMI, and the Multi-function

interrupt enable bit, EMF0I or EMF1I, must first be set. An actual Multi-function interrupt will take

place when the Multi-function interrupt request flag, MF0F or MF1F, is set. This will occur when

either a Time Base overflow, a Real Time Clock overflow, SIM0 or SIM 1 interrupt, an External

Peripheral Interrupt, Timer 2 overflow interrupt or Timer 3 overflow interrupt is generated. When the

interrupt is enabled and the stack is not full, and either one of the interrupts contained within the

Multi-function interrupts occurs, a subroutine call to the Multi-function interrupt vector at location

24H or 28H respectively will take place. When the interrupt is serviced, the Multi-Function request

flag, MF0F or MF1F, will be automatically reset and the EMI bit will be automatically cleared to

disable other interrupts. However, it must be noted that the request flags from the original source of the

Multi-function interrupt, namely the Time-Base interrupt, Real Time Clock interrupt, SIM interrupts,

External Peripheral interrupt, Timer 2 overflow interrupt or Timer 3 overflow interrupt will not be

automatically reset and must be manually reset by the application program.

Real Time Clock Interrupt

The Real Time Clock Interrupt is contained within the Multi-function 0 Interrupt.

For a Real Time Clock interrupt to be generated, the global interrupt enable bit, EMI, Real Time Clock

interrupt enable bit, ERTI, and Multi-function 0 interrupt enable bit, EMF0I, must first be set. An

actual Real Time Clock interrupt will take place when the Real Time Clock request flag, RTF, is set, a

situation that will occur when the Real Time Clock overflows. When the interrupt is enabled, the stack

is not full and the Real Time Clock overflows, a subroutine call to the Multi-function 0 interrupt vector

at location 24H, will take place. When the Real Time Clock interrupt is serviced, the EMI bit will be

cleared to disable other interrupts, however only the MF0F interrupt request flag will be reset. As the

RTF flag will not be automatically reset, it has to be cleared by the application program.

Similar in operation to the Time Base interrupt, the purpose of the RTC interrupt is also to provide an

interrupt signal at fixed time periods. The RTC interrupt clock source originates from the internal clock

source fS. This fS input clock first passes through a divider, the division ratio of which is selected by

programming the appropriate bits in the RTCC register to obtain longer RTC interrupt periods whose

value ranges from 28/fS~215/fS. The clock source that generates fS, which in turn controls the RTC

interrupt period, can originate from three different sources, the 32.768kHz oscillator (LXT), the

internal 32kHz RC oscillator (LIRC) or the System oscillator divided by 4 (fSYS/4), the choice of which

is determine by the fS clock source configuration option.

HT56RB688

TinyPowerTM A/D type Smart Card OTP MCU

with LCD, DAC, ISO 7816 and USB Interfaces

Rev. 1.10

April 15, 2013

f S S o u r c e

C o n f i g u r a t i o n

O p t i o n

f S Y S / 4

L X T

L I R C

D i v i d e b y 2 8 ~ 2 1 5

S e t b y R T C C

R e g i s t e r

f S

R T C I n t e r r u p t

2 1 2 / f S ~ 2 1 5 / f S

R T 2

R T 1

R T 0

RTC Interrupt

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