MAS3587F datasheet(15/82 Pages) MICRONAS

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ADVANCE INFORMATION

MAS 3587F

Micronas

2.12. MPEG Synchronization Output

The signal at pin SYNC is set to ‘1’ after the internal

decoding for the MPEG header has been finished for

one frame. The rising edge of this signal can be used

as an interrupt input for the controller that triggers the

read out of the control information and ancillary data.

As soon as the MAS 3587F has received the SYNC

reset command (see Section 3.3.1.12. ), the SYNC

signal is cleared. If the controller does not issue a

reset command, the SYNC signal returns to ’0’ as

soon as the decoding of the next MPEG frame is

started. MPEG status and ancillary data become

invalid until the frame is completely decoded and the

signal at pin SYNC rises again. The controller must

have finished reading all MPEG information before it

becomes invalid. The MPEG Layer2/3 frame lengths

are given in Table 2–2.

Fig. 2–10: Schematic timing of the signal at pin SYNC.

The signal is cleared at tread when the controller has

issued a Clear SYNC Signal command (see Section

3.3.1.12. ). If no command is issued, the signal returns

to ’0’ just before the decoding of the next MPEG frame.

2.13. Default Operation

This sections refers to the standard operation mode

”power-optimized solution” (see Section 2.9.3.).

2.13.1. Stand-by Functions

After applying the battery voltage, the system will

remain stand-by, as long as the DCEN pin level is kept

low. Due to the low stand-by current of CMOS circuits,

the battery may remain connected to DCSOn/VSENSn

at all times.

2.13.2. Power-Up of the DC/DC Converters

and Reset

The battery voltage must be applied to pin DCSOn via

the 22-µH inductor and, furthermore, to the sense pin

VSENSn via a Schottky diode (see Fig. 2–7 on

page 12).

For start-up, the pin DCEN must be connected via an

external “start” push button to the I2CVDD supply,

which is equivalent to the battery supply voltage

(> 0.9 V) at start-up.

The supply at DCEN must be applied until the DC/DC

converters have started up (signal at pin PUP) and

then removed for normal operation.

As soon as the output voltage at VSENSn reaches the

default voltage monitor reset level of 3.0 V, the respec-

tive internal PUPn bit will be set. When both PUPn bits

are set, the signal at pin PUP will go high and can be

used to start and reset the microcontroller.

Before transmitting any I2C commands, the controller

must issue a power-on reset to pin POR. The separate

supply pin I2CVDD assures that the I2C interface

works indepentently of the DSP or the audio codec.

Now the desired supply voltage can be programmed at

I2C subaddress 76hex (see Table 3–3 on page 20).

The signal at pin PUP will return to low only when both

PUPn flags (I2C subaddress 76hex) have returned to

zero. Care must be taken when changing both DC/DC

output voltages to higher values. In this case, both out-

put voltages are momentarily insufficient to keep the

PUPn flags up; the resulting dip in the signal at the

PUP pin may in turn reset the microcontroller. To avoid

this condition, only one DC/DC output voltage should

be changed at a time. Before modifying the second

voltage, the microcontroller must wait for the PUPn flag

of the first voltage to be set again.

The operating mode (pulse width modulation or pulse

frequency modulation, synchronized rectifier for higher

efficiency) are controlled at I2C subaddress 76hex, the

operating frequency at I2C subaddress 77hex.

Table 2–2: Frame length in MPEG Layer 2/3

fs/kHz

Frame Length

Layer 2

Frame Length

Layer 3

24 ms

44.1

26.12 ms

36 ms

24 ms

22.05

26.12 ms

36 ms

not available

48 ms

11.025

not available

52.24 ms

not available

72 ms

tread

tframe = 24...72 ms

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