MAS3587F datasheet(10/82 Pages) MICRONAS

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MAS 3587F

ADVANCE INFORMATION

Micronas

2.7.2.2. Balance and Volume

To minimize quantization noise, the main volume con-

trol is automatically split into a digital and an analog

part. The volume range is

−114...+12 dB with an addi-

tional mute position. A balance function is provided

(see Table 3–12 on page 43).

2.7.3. D/A Converters

A pair of Micronas’ unique multibit sigma-delta D/A

converters is used to convert the audio data with high

linearity and a superior S/N. In order to attenuate high-

frequency noise caused by noise-shaping, internal

low-pass filters are included. They require additional

external capacitors between pins FILTR and OUTR,

and FILTL and OUTL respectively (see Section 4.7. on

page 79).

2.7.4. Output Amplifiers

The integrated output amplifiers are capable of driving

stereo headphones of 16...32

Ω impedance via 22-Ω

series resistors or built-in loudspeakers of 16

Ω imped-

ance directly. If more output power is required, the right

output signal can be inverted and a single loudspeaker

can be connected as a bridge between pins OUTL and

OUTR. In this case the minimum impedance is 32 W,

and for optimized power the source should be set to

mono.

Fig. 2–6: Bridge operation mode

2.8. Clock Management

The MAS 3587F is driven by a single crystal-controlled

clock with a frequency of 18.432 MHz. It is possible to

drive the MAS 3587F with other reference clocks. In

this case, the nominal crystal frequency must be writ-

ten into memory location D0:7f3. The crystal clock acts

as a reference for the embedded synthesizer that gen-

erates the internal clock.

For compressed audio data reception, the MAS 3587F

may act either as the clock master (Demand Mode) or

as a slave (Broadcast Mode) as defined by bit 1 in

IOControlMain

memory

cell

(see

Table 3–7

page 34). In both modes, the output of the clock syn-

thesizer depends on the sample rate of the decoded

data stream as shown in Table 2–1.

In the BROADCAST MODE (PLL on), the incoming

audio data controls the clock synthesizer via a PLL.

In the DEMAND MODE (PLL off) the MAS 3587F acts

as the system master clock, the internal clock. The

data transfer is triggered by a demand signal at pin

EOD. This mode is used in most applications.

In the encoder application, the MAS 3587F is clock

master in case of I2S audio input. For S/PDIF input, the

MAS 3587F synchronizes the clock to the incomming

S/PDIF signal.

≥ 32 Ω

MASF

DAC

OUTL

OUTR

Table 2–1: Settings of bits 8 and 17 in OutClkConfig

and resulting CLKO output frequencies

fs/kHz

Output Frequency at CLKO/MHz

Synth.

Clock

bit 8=1

Scaler On

bit 8=0, bit 17=0

Scaler Plus

Extra Division

bit 8=0, bit 17=1

24.576

512

⋅f

24.576

256

⋅f

12.288

44.1

22.5792

11.2896

24.576

768

⋅f

24.576

384

⋅f

12.288

512

⋅f

12.288

256

⋅f

6.144

22.05

22.5792

11.2896

5.6448

24.576

768

⋅f

12.288

384

⋅f

6.144

512

⋅f

6.144

256

⋅f

3.072

11.025 22.5792

5.6448

2.8224

24.576

768

⋅f

6.144

384

⋅f

3.072

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