AN708

Vishay Siliconix

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4

Document Number: 70581

Therefore,

A 600 V MOSFET allows for a 150 V spike due to leakage

inductance at high line. The RC snubber was sized empirically

to keep the peak drain voltage below 600 V.

_C

peak drain current was previously calculated at 0.634 A. The

maximum RMS drain current is given by

I

D

3

1

0.5

3

+ 0.26 A

On-state losses are given by

W

= 237 mW.

Switching losses are estimated at 350 mW. Since the thermal

resistance is specified at 80

_C/W, a total temperature rise of

47

_C is expected. This permits operation up to approximately

50

_C ambient temperature, while holding the maximum

junction temperature to 100

_C.

Something of more concern for universal-input than for a

single-input voltage supply is the range of duty factor to be

expected. Since the on time varies inversely with input voltage,

the high-line on-time can become quite small in a

high-frequency converter. For this kind of application, try to

keep the minimum on time to not much less than 1

ms. This will

help minimize noise problems with the current sense.

Also, be sure to use a non-inductive resistor for the current

sense (carbon composition or film type). Use of a wire-wound

resistor will produce large spikes which have to be filtered out.

The dual-delay current-limit comparators of the Si9120 will

frequently eliminate the need for a current-sense filter

altogether. The magnitude of the noise on the current sense

voltage will be affected by transformer parasitic capacitances

and PCB layout. As such, every design will exhibit slightly

different characteristics. Careful attention to detail in the

magnetics design and construction as well as the board layout

is a must.

For designs using current-sense resistors in the power

MOSFET’s source leg, note that the gate drive current is “seen”

by the sense resistor. In very low-power designs, this can

easily exceed the full load sense voltage causing severe noise

problems. Adding a fairly large-value gate resistor will help in

this case. Also, an RC current-sense filter becomes much

more important.

FOLDBACK CIRCUIT

Foldback current limiting is provided by Q3 and its associated

components. Under normal operating conditions, diode D6

event of a short circuit on any output, all winding voltages are

clamped low. This causes the voltage on C13 to drop to a level

start-up regulator. The current set by the value of R12 flows

through Q3 and R3, and causes the voltage on pin 4 to rise.

Since a peak threshold of 1.2 V is internally set on pin 4, the

voltage required across R5 to terminate a pulse is reduced by

an amount equal to the drop on R3.

See Figure 2a for foldback operating waveforms.

The foldback circuit will not perform correctly without the spike

blanking circuit. The leakage spike will peak charge C13 even

with a shorted load. However, the foldback function is

completely optional and all associated components can be

eliminated if a lower cost supply is desired.

TEST RESULTS

Data compiled on the test circuit appear in Table 1. Combined

line and load regulation measures

"2.7%, well within a "5%

specification. Measured efficiency is 73.4% with no effort at

optimization. A detailed loss assessment could, no doubt, offer

some improvements. Pulse load tests show reasonable

transient response, and phase margin is measured at

60 degrees. For details on how to close the feedback loop,

refer to Vishay Siliconix application notes AN713 and AN707.

All data taken with dc input source to ensure stable readings.

TABLE 1. UNIVERSALINPUT SUPPLY

TEST DATA

Full Load:

+5 V

+12 V

–12 V

100 V

143.9

4.974

12.64

12.50

200 V

72.3

5.014

12.76

12.61

300 V

48.9

5.027

12.79

12.65

385 V

39.4

5.049

12.81

12.67

Half Load:

100 V

78.0

5.153

12.99

12.83

200 V

40.3

5.205

13.10

12.96

300 V

27.9

5.235

13.12

12.97

385 V

23.0

5.254

13.14

13.01

PKPK OUTPUT RIPPLE VOLTAGES

(SPIKES NOT INCLUDED)

5 V

+12 V

–12 V

60 mV

45 mV

40 mV

Note: Worst case over full line-voltage range.