AN708

Vishay Siliconix

Document Number: 70581

www.vishay.com

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5

Q1 Gate Drive (5 V/Div)

Q1 Gate Voltage (100 V/Div)

Q1 Drain Voltage (100 V/Div)

Q1 Drain Voltage (100 V/Div)

a)

b)

c)

Short Circuit On 5 V Output

Voltage On U1, Pin 4 (Current Sense)

(0.5 V/Div)

NOTE: 0.8 V dc pedestal caused by

Voltage On U1, Pin 4 (Current Sense)

(0.5 V/Div)

the foldback circuit.

During testing, an input capacitor value of as little as 33

mF

proved adequate versus the design value of 68

mF. The

low-value capacitor produces an input ripple voltage of 30 V

pk-pk. Since the primary inductance is slightly lower than the

design maximum value, the circuit is still able to maintain

regulation with the higher input ripple voltage value. This is a

good example of where trade-offs can be made during

development programs. By using the larger input capacitance

and primary inductance, the peak input current could be

reduced slightly, and a slight improvement in efficiency should

result. However, a larger input capacitance will decrease the

conduction angle of the input rectifiers, and consequently will

reduce the input power factor. The priorities of a particular

application will determine the optimal approach.