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MPC823 датащи(PDF) 54 Page - Freescale Semiconductor, Inc

номер детали MPC823
подробное описание детали  This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC823.
PDF  70 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC823 датащи(HTML) 54 Page - Freescale Semiconductor, Inc

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MPC823 ELECTRICAL SPECIFICATIONS
Table 15. Ethernet Timing
NUM
CHARACTERISTIC
25MHZ
40MHZ
50MHZ
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
120
CLSN (CTS2) width high
40
Ñ
40
Ñ
40
Ñ
ns
121
RCLK1 rise and fall times
Ñ
15
Ñ
15
Ñ
15
ns
122
RCLK1 width low
40
Ñ
40
Ñ
40
Ñ
ns
123
RCLK1 clock period1
80
120
80
120
80
120
ns
124
RXD2 setup time
20
Ñ
20
Ñ
20
Ñ
ns
125
RXD2 hold time
5Ñ5Ñ5Ñ
ns
126
RENA (CD2) active delay (from RCLK1
rising edge of the last data bit)
10Ñ10Ñ10Ñ
ns
127
RENA (CD2) width low
100
Ñ
100
Ñ
100
Ñ
ns
128
TCLK1 rise and fall times
Ñ
15
Ñ
15
Ñ
15
ns
129
TCLK1 width low
40
Ñ
40
Ñ
40
Ñ
ns
130
TCLK1 clock period
1
99
101
99
101
99
101
ns
131
TXD2 active delay (from TCLK1 rising edge)
10
50
10
50
10
50
ns
132
TXD2 inactive delay (from TCLK1 rising
edge)
10
50
10
50
10
50
ns
133
TENA (RTS2) active delay (from TCLK1
rising edge)
10
50
10
50
10
50
ns
134
TENA (RTS2) inactive delay (from TCLK1
rising edge)
10
50
10
50
10
50
ns
135
N/A
136
N/A
137
N/A
138
CLKx low to SDACK asserted2
Ñ20Ñ20Ñ20
ns
139
CLKx low to SDACK negated3
Ñ20Ñ20Ñ20
ns
NOTES:
1.
The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1.
2.
SDACK is asserted when the SDMA writes the incoming frame DA into memory.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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