LT4220IGN datasheet(12/16 Pages) LINER

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LT4220

4220f

APPLICATIO S I FOR ATIO

Whenever the output voltages reach their final value as

sensed by R9, R10 and R11, R12 and both gate signals are

fully on, the PWRGD pin will go high impedance.

A typical timing sequence is shown in Figure 8 with

tracking enabled. The sequence is as follows:

1) The power pins make contact and the undervoltage

lockout thresholds are exceeded.

2) The ON comparator thresholds are exceeded and the

GATE pins start ramping up. VOUT+ follows GATE+ by

the N-channel FET threshold voltage.

3) GATE+ is limited by the tracking circuit because VOUT–

lags behind VOUT+. When VOUT– starts ramping, GATE–

holds at approximately the threshold voltage of the

N-channel FET due to C2 slew rate control.

4) When the magnitude of VOUT– catches up with VOUT+,

GATE+ resumes ramping. The slowest VOUT will limit

the faster VOUT slew rate.

5) GATE+ internal gate good signal threshold is reached.

6) GATE– internal gate good signal threshold is reached,

enabling the FB output comparators. If both FB com-

parators indicate the output is good, the PWRGD pin

output goes high impedance and is pulled up by an

external pullup resistor.

Power Supply Ramping

For large capacitive loads, the inrush current will be limited

by the VOUT+ and VOUT– slew rate or by the fold-back

current limit. For a desired inrush current that is less than

the fold-back current limit, the feedback networks R6, C1

and R8, C2 can be used to control the VOUT slew rate. For

the desired inrush current and typical gate pull-up current,

the feedback network capacitors C1 and C2 can be calcu-

lated as:

C1 = (10

µA • CL1)/IINRUSH+ and

(1)

C2 = (10

µA • CL2)/IINRUSH–

(2)

where CL1 and CL2 are the positive and negative output

load capacitance. If the supply-tracking mode is enabled

(TRACK = High), during startup, the output with the

slowest slew rate will also limit the slew rate of the

opposite output (Note: Supply-tracking is also controlled

by the resistive dividers on the FB pins. See Supply

Tracking). Additionally, C1 and C2 should be greater than

5nF to prevent large overshoot in the output voltage for

transient loads with small capacitive loads.

Capacitor C3 and resistor R8 prevent Q2 from momen-

tarily turning on when the power pins first make contact.

Without C3, capacitor C2 and CGD(Q2) would hold the gate

of Q2 near ground before the LT4220 could power up and

pull the gate low. The minimum required value of C3 can

be calculated by:

GD Q

1 2

−













() • .

()

(3)

where VTH is the MOSFET’s minimum gate threshold and

VEEMAX is the maximum negative supply input voltage. If

C2 is not used, the minimum value for C3 should be 10nF

to ensure stability. C2 and C3 must be the same type to

ensure tracking over temperature.

+UVLO

–UVLO

3 4

VCC

VEE

ON+

ON–

GATE+

VOUT+

GATE–

VOUT–

PWRGD

4220 F08

Figure 8. Typical Timing Sequence

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