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Revision 1.2

15 - 27

AS3935

Datasheet - Detailed Descri p ti on

8.4.2 Writing of Register Data

Figure 14. SPI Page Write

8.4.3 Reading of Data from Addressable Registers (READ Mode)

Once the address has been sent via SPI, the data can be fed through the MISO pin out to the microcontroller.

A CS high toggling high-low-high has to be performed after finishing the read mode session, in order to indicate the end of the READ command

and prepare the Interface to the next command control Byte.

To transfer bytes from consecutive addresses, SPI master has to keep the CS signal low and the SCLK clock has to be active as long as data

need to be read.

Figure 15. SPI Read Byte

CS

SCLK

MOSI

00 A5

A

4

A

3

A

2

A

1

A

0

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

X

X

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

1

Two leading

Zeros indicate

WRITE Mode

Data is moved

to Address

<A5-A0 >

Data is moved

to Address

<A5-A0 > + 1

Data is moved

to Address

<A5-A0 > + (n-1)

Data is moved

to Address

<A5-A0 > + n

CS falling

edge signals

end of

WRITE Mode

D

0

CS

SCLK

MOSI

0

1

A5

A4

A3

A2

A1

A0

X

X

D4

D3

D2

D1

D0

D7

D6

X

X

MISO

D5

SCLK rising

edge Data is

transferred from

µC

01pattern

indicates

READ Mode

SCLK

falling edge

Data is

sampled

SCLK rising

edge Data is

moved from

Address

<A5-A0>

SCLK falling

edge Data is

transferred to

µC

CS falling

edge signals

end of READ

Mode