AS8C401800 datasheet(9/17 Pages) ALSC

9 / 17 page

6.42

AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial Temperature Range

Linear Burst Sequence Table (LBO=VSS)

Synchronous Write Function Truth Table(1, 2)

Asynchronous Truth Table(1)

Interleaved Burst SequenceTable (LBO=VDD)

NOTES:

1. L = V IL, H = V IH, X = Don’t Care.

2. BW3 andBW4 are not applicable for the AS8C401800.

3. Multiple bytes may be selected during the same cycle.

NOTES:

1. L = V IL, H = V IH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

Operation

BWE

BW1

BW2

BW3

BW4

Read

HHX

Read

Write all Bytes

Write Byte 1(3)

Write Byte 2(3)

Write Byte 3(3)

HHL

Write Byte 4(3)

5279 tbl 12

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address(1)

5279 tbl 15

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address(1)

111

5279 tbl 14

Operation(2)

I/O Status

Power

Read

Data Out

Active

Read

High-Z

Active

Write

High-Z – Data In

Active

Deselected

High-Z

Standby

Sleep Mode

High-Z

Sleep

5279 tbl 13

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