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AS8C403600, AS8C401800, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial Temperature Range

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination of the rising edge

of CLK and ADSC Lo w o r ADSP Low and CE Lo w.

ADSC

Address Status

(Cache Controller)

ILOW

Synchronous Address Status from Cache Controller. ADSC is an active LOWinputthatis used to load

the address registers with new addresses.

ADSP

Address Status

(Processor)

ILOW

Synchronous Address Status from Processor. ADSP is an ac tive LOW input that is us ed to load the

address registers with new addresses. ADSP is gated by CE.

ADV

Burst Address

Advance

ILOW

Synchronous Address Advance. ADV is an active LOW inputthatis used to advance the internal

burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the

burstc ounter is noti ncremented; thatis, there is no address advance.

BWE

Byte Write Enable

I

LOW

edge of CLK then BWx inputs are p assed to the nextstage in the circuit. If BWE is HIGH then the

byte write inputs are blocked and only GW c an initiate a w rite cycle.

Individual Byte

Write Enables

ILOW

active byte write causes all outputs to be disabled.

CE

Chip Enable

I

LOW

ADSP

.

CLK

Clock

I

N/A

This is the clock i nput. A ll timing references fo r the d evice are made with respectto this input.

Chip Select 0

I

HIGH

Chip Select 1

I

LOW

GW

Global Write

Enable

ILOW

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising

edge of CLK. GW supersedes individual byte write enables.

Data Input/Output

I/O

N/A

Synchronous d ata input/output(I/O) p ins. B oth the d ata inputp ath and d ata o utputp ath are registered

and triggered by the rising edge of CLK.

LBO

Linear Burst Order

I

LOW

Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is

selected. When LBO is LOW the Linear burst sequence is selected. LBO is a s tatic input and must

not change state while the device is operating.

OE

Output Enable

I

LOW

Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if

the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.

TMS

Test ModeSelect

I

N/A

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal

pullup.

TDI

TestData Input

I

N/A

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has

an internal pullup.

TCK

TestClock

I

N/A

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of

TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TDO

TestDataOutput

O

N/A

Serial output of registers placed between TDI and TDO. This output is active depending on the state

of the TAP controller.

ZZ

Sleep Mode

I

HIGH

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

AS8C403600/1800 to its lowest power consumption level. Data retention is guaranteed in Sleep

Mode.This pin has an internal pull down.

Power Supply

N/A

N/A

3.3V c ore p ower supply.

Power Supply

N/A

N/A

3.3V I/O Supply.

Ground

N/A

N/A

Ground.

NC

No Connect

N/A

N/A

NC pins are note lectrically connected to the d evice.

5279 tbl 02