PIN CONFIGURATION

A1

A2

A3

A4

DQ15

DQ0

DQ1

DQ2

Vcc

Vss

A13

A18

DQ14

DQ12

DQ13

DQ11

Vss

Vcc

DQ10

DQ9

DQ3

DQ4

TSOP II

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

A17

A0

DQ6

DQ7

A5

A6

A7

A9

A10

DQ5

DQ8

A16

A15

A14

A11

A8

34

29

30

31

32

33

44

39

40

41

42

43

35

36

37

38

A12

CE#

WE#

LB#

UB#

OE#

TFBGA

NC

A3

A10

A9

A11

A0

A14

A8

NC

WE#

DQ9

DQ14

DQ15

A18

Vss

NC

A13

DQ8

Vcc

Vcc

DQ7

A15

Vss

CE#

LB#

DQ6

DQ2

DQ0

A2

OE#

A1

A6

A5

A4

UB#

1

2

3

4

5

6

H

G

C

D

E

F

A

B

A12

NC

A17

A7

A16

DQ10

DQ11

DQ12

DQ13

DQ5

DQ4

DQ3

DQ1

ABSOLUTE MAXIMUN RATINGS*

PARAMETER

SYMBOL

RATING

UNIT

-0.5 to 6.5

V

V

Operating Temperature

-40 to 85(I grade)

℃

Storage Temperature

-65 to 150

℃

Power Dissipation

1

W

DC Output Current

50

mA

Soldering Temperature (under 10 sec)

260

℃

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

512K X 8 BIT LOW POWER CMOS SRAM

January 2007

NOVEMBER 2007

NOVEMBER/2007, V 1.0

Alliance Memory Inc.

Page 2 of 12

AS6C8016

512K X 16 BIT SUPER LOW POWER CMOS SRAM