AS4C64M8D2 datasheet(30/59 Pages) ALSC

30 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

NOTE 17: ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is

when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed

bin. For DDR2-667/800, if tCK (avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing

clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input

clock edges.

NOTE 18: tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are

referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or

begins driving (tLZ).

NOTE 19: tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the

device output is no longer driving (tRPST), or begins driving (tRPRE). The actual voltage measurement points are

not critical as long as the calculation is consistent.

NOTE 20: Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input

signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the

input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to

the device under test. DQS, DQS# signals must be monotonic between VIL(dc)max and VIH(dc)min.

NOTE 21: Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the

differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and from

the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied

to the device under test. DQS, DQS# signals must be monotonic between VIL(dc)max and VIH(dc)min.

NOTE 22: Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal

and VIL(ac) for a falling signal applied to the device under test.

NOTE 23: Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal

and VIH(dc) for a falling signal applied to the device under test.

NOTE 24: tWTR is at lease two clocks (2 x tCK ) independent of operation frequency.

NOTE 25: tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must

remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any

CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH.

NOTE 26: If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a

valid READ can be executed.

NOTE 27: These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#, ODT,

BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec values are not

affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to

the clock signal crossing that latches the command/address. That is, these parameters should be met whether

clock jitter is present or not.

NOTE 28: These parameters are measured from a data strobe signal (DQS/DQS#) crossing to its respective clock

signal (CK/CK#) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per),

tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met

whether clock jitter is present or not.

NOTE 29: These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its

respective data strobe signal (DQS/DQS#) crossing.

NOTE 30: For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM =

RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied.

NOTE 31: tDAL [tCK] = WR [tCK] + tRP [tCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed

in the mode register set.

NOTE 32: New units, ‘tCK(avg)’ is introduced in DDR2-667 and DDR2-800. Unit ‘tCK(avg)’ represents the actual

tCK(avg) of the input clock under operation.

NOTE 33: Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as

'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter

specified is a random jitter meeting a Gaussian distribution.

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