Timing Diagrams

ENABLE vs CLOCK

TLF7511 – 9

CLOCK vs DATA

TLF7511 – 10

AMFM Frequency Synthesizer (Scan Mode)

TLF7511 – 11

Timing diagrams are not drawn to scale Scale within any one drawing may not be consistent and intervals are defined positive as drawn

SERIAL DATA ENTRY INTO THE DS8907

Serial information entry into the DS8907 is enabled by a low

level on the ENABLE input One binary bit is then accepted

from the DATA input with each positive transition of the

CLOCK input The CLOCK input must be low for the speci-

fied time preceding and following the negative transition of

the ENABLE input

The first two bits accepted following the negative transition

of the ENABLE input are interpreted as address If these

address bits are

not 11 no further information will be ac-

cepted from the DATA inputs and the internal data latches

will not be changed when ENABLE returns high

If these first two bits

are 11 then all succeeding bits are

accepted as data and are shifted successively into the in-

ternal shift register as long as ENABLE remains low

Any data bits preceding the 18th to last bit will be shifted

out and thus are irrelevant Data bits are counted as any

bits

following two valid address bits (11) with the ENABLE

low When the ENABLE input returns high any further serial

data entry is inhibited Upon this positive transition the data

in the internal shift register is transferred into the internal

data latches Note that until this time the states of the inter-

nal data latches have remained unchanged

These data bits are interpreted as follows

Data Bit Position

Data Interpretation

Last

Bit 18 Output (Pin 2)

2nd to Last

Bit 17 Output (Pin 1)

3rd to Last

Bit 16 Output (FMAM) (Pin 20)

4th to Last

Bit 15 Output (Pin 19)

5th to Last

Bit 14 Output (Pin 18)

6th to Last

7th to Last

8th to Last

9th to Last

10th to Last

11th to Last

12th to Last

d

N

13th to Last

14th to Last

15th to Last

16th to Last

17th to Last

18th to Last

-

Note

4