STM32L471RG datasheet(50/218 Pages) STMICROELECTRONICS

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Functional overview

STM32L471xx

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DocID027226 Rev 1

3.28

Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s

slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8

master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI

interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

3.29

Serial audio interfaces (SAI)

The device embeds 2 SAI. Refer to Table 13: SAI implementation for the features

implementation. The SAI bus interface handles communications between the

microcontroller and the serial audio protocol.

The SAI peripheral supports:

•

Two independent audio sub-blocks which can be transmitters or receivers with their

respective FIFO.

•

8-word integrated FIFOs for each audio sub-block.

•

Synchronous or asynchronous mode between the audio sub-blocks.

•

Master or slave configuration independent for both audio sub-blocks.

•

Clock generator for each audio block to target independent audio frequency sampling

when both audio sub-blocks are configured in master mode.

•

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

•

Peripheral with large configurability and flexibility allowing to target as example the

following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF

out.

•

Up to 16 slots available with configurable size and with the possibility to select which

ones are active in the audio frame.

•

Number of bits by frame may be configurable.

•

Frame synchronization active level configurable (offset, bit length, level).

•

First active bit position in the slot is configurable.

•

LSB first or MSB first for data transfer.

•

Mute mode.

•

Stereo/Mono audio frame capability.

•

Communication clock strobing edge configurable (SCK).

•

Error flags with associated interrupts if enabled respectively.

–

Overrun and underrun detection.

–

Anticipated frame synchronization signal detection in slave mode.

–

Late frame synchronization signal detection in slave mode.

–

Codec not ready for the AC’97 mode in reception.

•

Interruption sources when enabled:

–Errors.

–

FIFO requests.

•

DMA interface with 2 dedicated channels to handle access to the dedicated integrated

FIFO of each SAI audio sub-block.

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