STM32L431 datasheet(46/200 Pages) STMICROELECTRONICS

46 / 200 page

Functional overview

STM32L431xx

46/200

DocID028800 Rev 1

•

Transmission

–

Three transmit mailboxes

–

Configurable transmit priority

•

Reception

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Two receive FIFOs with three stages

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14 Scalable filter banks

–

Identifier list feature

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Configurable FIFO overrun

•

Time-triggered communication option

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Disable automatic retransmission mode

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16-bit free running timer

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Time Stamp sent in last two data bytes

•

Management

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Maskable interrupts

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Software-efficient mailbox mapping at a unique address space

3.31

Secure digital input/output and MultiMediaCards Interface

(SDMMC)

The card host interface (SDMMC) provides an interface between the APB peripheral bus

and MultiMediaCards (MMCs), SD memory cards and SDIO cards.

The SDMMC features include the following:

•

Full compliance with MultiMediaCard System Specification Version 4.2. Card support

for three different databus modes: 1-bit (default), 4-bit and 8-bit

•

Full compatibility with previous versions of MultiMediaCards (forward compatibility)

•

Full compliance with SD Memory Card Specifications Version 2.0

•

Full compliance with SD I/O Card Specification Version 2.0: card support for two

different databus modes: 1-bit (default) and 4-bit

•

Data transfer up to 48 MHz for the 8 bit mode

•

Data write and read with DMA capability

3.32

Clock recovery system (CRS)

The STM32L431xx devices embed a special block which allows automatic trimming of the

internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device

operational range. This automatic trimming is based on the external synchronization signal,

which could be either derived from LSE oscillator, from an external signal on CRS_SYNC

pin or generated by user software. For faster lock-in during startup it is also possible to

combine automatic trimming with manual trimming action.

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