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STM32L162VC датащи(PDF) 75 Page - STMicroelectronics |
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STM32L162VC датащи(HTML) 75 Page - STMicroelectronics |
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75 / 123 page ![]() DocID022881 Rev 10 75/123 STM32L162VC, STM32L162RC 104 6.3.8 PLL characteristics The parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 14. 6.3.9 Memory characteristics The characteristics are given at TA = -40 to 105 °C unless otherwise specified. RAM memory Table 34. PLL characteristics Symbol Parameter Value Unit Min Typ Max(1) 1. Guaranteed by characterization results. fPLL_IN PLL input clock(2) 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 2- 24 MHz PLL input clock duty cycle 45 - 55 % fPLL_OUT PLL output clock 2 - 32 MHz tLOCK PLL lock time PLL input = 16 MHz PLL VCO = 96 MHz -115 160 µs Jitter Cycle-to-cycle jitter - - ±600 ps IDDA(PLL) Current consumption on VDDA -220 450 µA IDD(PLL) Current consumption on VDD -120 150 Table 35. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode(1) 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). STOP mode (or RESET) 1.65 - - V |
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