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STM32F042F4 датащи(PDF) 79 Page - STMicroelectronics |
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STM32F042F4 датащи(HTML) 79 Page - STMicroelectronics |
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79 / 117 page ![]() DocID025832 Rev 5 79/117 STM32F042x4 STM32F042x6 Electrical characteristics 89 fTRIG(2) External trigger frequency fADC = 14 MHz, 12-bit resolution -- 823 kHz 12-bit resolution - - 17 1/fADC VAIN Conversion voltage range - 0 - VDDA V RAIN(2) External input impedance See Equation 1 and Table 55 for details -- 50 kΩ RADC(2) Sampling switch resistance -- - 1 kΩ CADC(2) Internal sample and hold capacitor -- - 8 pF tCAL(2)(3) Calibration time fADC = 14 MHz 5.9 µs -83 1/fADC WLATENCY(2)(4) ADC_DR register ready latency ADC clock = HSI14 1.5 ADC cycles + 2 fPCLK cycles - 1.5 ADC cycles + 3 fPCLK cycles - ADC clock = PCLK/2 - 4.5 - fPCLK cycle ADC clock = PCLK/4 - 8.5 - fPCLK cycle tlatr(2) Trigger conversion latency fADC = fPCLK/2 = 14 MHz 0.196 µs fADC = fPCLK/2 5.5 1/fPCLK fADC = fPCLK/4 = 12 MHz 0.219 µs fADC = fPCLK/4 10.5 1/fPCLK fADC = fHSI14 = 14 MHz 0.179 - 0.250 µs JitterADC ADC jitter on trigger conversion fADC = fHSI14 -1 - 1/fHSI14 tS(2) Sampling time fADC = 14 MHz 0.107 - 17.1 µs - 1.5 - 239.5 1/fADC tSTAB(2) Stabilization time - 14 1/fADC tCONV(2) Total conversion time (including sampling time) fADC = 14 MHz, 12-bit resolution 1- 18 µs 12-bit resolution 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA on IDD should be taken into account. 2. Guaranteed by design, not tested in production. 3. Specified value includes only ADC timing. It does not include the latency of the register access. 4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time. Table 54. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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