| поискавой системы для электроныых деталей |
|
STM32F042F4 датащи(PDF) 60 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32F042F4 датащи(HTML) 60 Page - STMicroelectronics |
|
60 / 117 page ![]() Electrical characteristics STM32F042x4 STM32F042x6 60/117 DocID025832 Rev 5 6.3.6 Wakeup time from low-power mode The wakeup times given in Table 33 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture. The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode. During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz. The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode. The wakeup source from Standby mode is the WKUP1 pin (PA0). All timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.. 6.3.7 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 15: High-speed external clock source AC timing diagram . Table 33. Low-power mode wakeup timings Symbol Parameter Conditions Typ @VDD = VDDA Max Unit = 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V tWUSTOP Wakeup from Stop mode Regulator in run mode 3.23.1 2.92.9 2.8 5 µs Regulator in low power mode 7.05.8 5.24.9 4.6 9 tWUSTANDBY Wakeup from Standby mode - 60.4 55.6 53.5 52 51 - tWUSLEEP Wakeup from Sleep mode - 4 SYSCLK cycles - Table 34. High-speed external user clock characteristics Symbol Parameter(1) Min Typ Max Unit fHSE_ext User external clock source frequency - 8 32 MHz VHSEH OSC_IN input pin high level voltage 0.7 VDDIOx -VDDIOx V VHSEL OSC_IN input pin low level voltage VSS - 0.3 VDDIOx tw(HSEH) tw(HSEL) OSC_IN high or low time 15 - - ns tr(HSE) tf(HSE) OSC_IN rise or fall time - - 20 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |